9d035fa1f7
Same comments were already removed for the latest board, the amd/lamar. Change-Id: Ie244f838409c567c11f7444c9cf17de72e49dbb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10283 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
132 lines
4.6 KiB
C
132 lines
4.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include "AGESA.h"
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#include "amdlib.h"
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#include "Ids.h"
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#include "heapManager.h"
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#include "PlatformGnbPcieComplex.h"
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#include "Filecode.h"
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#include <string.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
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/*---------------------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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*
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* Description:
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* This stub function will call the host environment through the binary block
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* interface (call-out port) to provide a user hook opportunity
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*
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* Parameters:
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* @param[in] *InitEarly
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*
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* @retval VOID
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*
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**/
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/*---------------------------------------------------------------------------------------*/
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static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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{
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AGESA_STATUS Status;
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VOID *BrazosPcieComplexListPtr;
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VOID *BrazosPciePortPtr;
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VOID *BrazosPcieDdiPtr;
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ALLOCATE_HEAP_PARAMS AllocHeapParams;
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PCIe_PORT_DESCRIPTOR PortList [] = {
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// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
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},
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// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
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}
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};
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PCIe_DDI_DESCRIPTOR DdiList [] = {
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// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
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//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
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{ConnectorTypeDP, Aux1, Hdp1}
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},
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// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
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//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
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{ConnectorTypeDP, Aux2, Hdp2}
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}
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};
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PCIe_COMPLEX_DESCRIPTOR Brazos = {
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DESCRIPTOR_TERMINATE_LIST,
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0,
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&PortList[0],
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&DdiList[0]
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};
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// GNB PCIe topology Porting
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//
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// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
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//
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AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
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AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
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AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
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Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
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ASSERT(Status == AGESA_SUCCESS);
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BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
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AllocHeapParams.BufferPtr += sizeof(Brazos);
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BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
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AllocHeapParams.BufferPtr += sizeof(PortList);
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BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
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memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
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memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
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memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
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((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
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((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
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InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
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InitEarly->GnbConfig.PsppPolicy = 0;
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return AGESA_SUCCESS;
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}
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const struct OEM_HOOK OemCustomize = {
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.InitEarly = OemInitEarly,
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};
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