9dd27bc03a
Kconfig) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
135 lines
3.1 KiB
Plaintext
135 lines
3.1 KiB
Plaintext
uses CONFIG_SANDPOINT_ALTIMUS
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uses CONFIG_CBFS
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uses CONFIG_ARCH_X86
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uses CONFIG_SANDPOINT_TALUS
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uses CONFIG_SANDPOINT_UNITY
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uses CONFIG_SANDPOINT_VALIS
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uses CONFIG_SANDPOINT_GYRUS
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uses CONFIG_ISA_IO_BASE
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uses CONFIG_ISA_MEM_BASE
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uses CONFIG_PCIC0_CFGADDR
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uses CONFIG_PCIC0_CFGDATA
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uses CONFIG_PNP_CFGADDR
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uses CONFIG_PNP_CFGDATA
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uses CONFIG_IO_BASE
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uses CONFIG_CROSS_COMPILE
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uses CONFIG_HAVE_OPTION_TABLE
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uses CONFIG_SANDPOINT_ALTIMUS
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uses CONFIG_COMPRESS
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uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_USE_INIT
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uses CONFIG_CHIP_CONFIGURE
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uses CONFIG_NO_POST
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_TTYS0_BASE
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uses CONFIG_IDE
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uses CONFIG_FS_PAYLOAD
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uses CONFIG_FS_EXT2
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uses CONFIG_FS_ISO9660
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uses CONFIG_FS_FAT
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uses CONFIG_AUTOBOOT_CMDLINE
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uses CONFIG_PAYLOAD_SIZE
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uses CONFIG_ROM_SIZE
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uses CONFIG_ROM_IMAGE_SIZE
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uses CONFIG_RESET
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uses CONFIG_EXCEPTION_VECTORS
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uses CONFIG_ROMBASE
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uses CONFIG_ROMSTART
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uses CONFIG_RAMBASE
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uses CONFIG_RAMSTART
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uses CONFIG_STACK_SIZE
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uses CONFIG_HEAP_SIZE
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uses CONFIG_MAINBOARD
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uses CONFIG_MAINBOARD_VENDOR
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uses CONFIG_MAINBOARD_PART_NUMBER
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uses COREBOOT_EXTRA_VERSION
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uses CONFIG_CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses CONFIG_OBJCOPY
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##
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## Set memory map
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##
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default CONFIG_ISA_IO_BASE=0xfe000000
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default CONFIG_ISA_MEM_BASE=0xfd000000
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default CONFIG_PCIC0_CFGADDR=0xfec00000
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default CONFIG_PCIC0_CFGDATA=0xfee00000
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default CONFIG_PNP_CFGADDR=0x15c
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default CONFIG_PNP_CFGDATA=0x15d
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default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE
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##
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## The default compiler
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##
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default CC="$(CONFIG_CROSS_COMPILE)gcc"
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default HOSTCC="gcc"
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## use a cross compiler
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#default CONFIG_CROSS_COMPILE="powerpc-eabi-"
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#default CONFIG_CROSS_COMPILE="ppc_74xx-"
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default CONFIG_ARCH_X86=0
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## Use stage 1 initialization code
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default CONFIG_USE_INIT=1
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## Use static configuration
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default CONFIG_CHIP_CONFIGURE=1
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## We don't use compressed image
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default CONFIG_COMPRESS=0
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## Turn off POST codes
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default CONFIG_NO_POST=1
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## Enable serial console
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default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
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default CONFIG_CONSOLE_SERIAL8250=1
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default CONFIG_TTYS0_BASE=0x3f8
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## Load payload using filo
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default CONFIG_IDE=1
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default CONFIG_FS_PAYLOAD=1
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default CONFIG_FS_EXT2=1
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default CONFIG_FS_ISO9660=1
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default CONFIG_FS_FAT=1
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default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
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# coreboot must fit into 128KB
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default CONFIG_ROM_IMAGE_SIZE=131072
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default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE}
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default CONFIG_PAYLOAD_SIZE=262144
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# Set stack and heap sizes (stage 2)
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default CONFIG_STACK_SIZE=0x10000
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default CONFIG_HEAP_SIZE=0x10000
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# Sandpoint Demo Board
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## Base of ROM
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default CONFIG_ROMBASE=0xfff00000
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## Sandpoint reset vector
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default CONFIG_RESET=CONFIG_ROMBASE+0x100
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## Exception vectors (other than reset vector)
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default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
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## Start of coreboot in the boot rom
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## = CONFIG_RESET + exeception vector table size
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default CONFIG_ROMSTART=CONFIG_RESET+0x3100
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## Coreboot C code runs at this location in RAM
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default CONFIG_RAMBASE=0x00100000
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default CONFIG_RAMSTART=0x00100000
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default CONFIG_SANDPOINT_ALTIMUS=1
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### End Options.lb
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#
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# CBFS
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#
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#
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default CONFIG_CBFS=0
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end
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