9dd27bc03a
Kconfig) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
145 lines
2.9 KiB
Plaintext
145 lines
2.9 KiB
Plaintext
uses CONFIG_HAVE_MP_TABLE
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uses CONFIG_CBFS
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uses CONFIG_HAVE_PIRQ_TABLE
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uses CONFIG_USE_FALLBACK_IMAGE
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uses CONFIG_HAVE_FALLBACK_BOOT
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uses CONFIG_HAVE_HARD_RESET
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uses CONFIG_HAVE_OPTION_TABLE
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uses CONFIG_USE_OPTION_TABLE
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uses CONFIG_COMPRESS
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_USE_INIT
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uses CONFIG_IRQ_SLOT_COUNT
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uses CONFIG_MAINBOARD
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uses CONFIG_MAINBOARD_VENDOR
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uses CONFIG_MAINBOARD_PART_NUMBER
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uses COREBOOT_EXTRA_VERSION
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uses CONFIG_ARCH
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uses CONFIG_FALLBACK_SIZE
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uses CONFIG_STACK_SIZE
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uses CONFIG_HEAP_SIZE
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uses CONFIG_ROM_SIZE
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uses CONFIG_ROM_SECTION_SIZE
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uses CONFIG_ROM_IMAGE_SIZE
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uses CONFIG_ROM_SECTION_SIZE
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uses CONFIG_ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses CONFIG_PAYLOAD_SIZE
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uses CONFIG_ROMBASE
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uses CONFIG_RAMBASE
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uses CONFIG_XIP_ROM_SIZE
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uses CONFIG_XIP_ROM_BASE
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uses CONFIG_HAVE_MP_TABLE
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uses CONFIG_CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses CONFIG_OBJCOPY
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uses CONFIG_TTYS0_BAUD
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uses CONFIG_TTYS0_BASE
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uses CONFIG_TTYS0_LCS
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default CONFIG_TTYS0_BAUD=115200
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#default CONFIG_TTYS0_BAUD=57600
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#default CONFIG_TTYS0_BAUD=38400
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#default CONFIG_TTYS0_BAUD=19200
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#default CONFIG_TTYS0_BAUD=9600
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#default CONFIG_TTYS0_BAUD=4800
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#default CONFIG_TTYS0_BAUD=2400
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#default CONFIG_TTYS0_BAUD=1200
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# Select the serial console base port
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default CONFIG_TTYS0_BASE=0x2f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default CONFIG_TTYS0_LCS=0x3
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default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
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default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
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## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
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default CONFIG_ROM_SIZE = 256*1024
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default CONFIG_HAVE_FALLBACK_BOOT=1
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##
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## no MP table
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##
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default CONFIG_HAVE_MP_TABLE=0
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##
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## Build code to reset the motherboard from coreboot
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##
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default CONFIG_HAVE_HARD_RESET=0
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##
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## Build code to export a programmable irq routing table
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##
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default CONFIG_HAVE_PIRQ_TABLE=1
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default CONFIG_IRQ_SLOT_COUNT=7
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#object irq_tables.o
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##
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## Build code to export a CMOS option table
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##
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default CONFIG_HAVE_OPTION_TABLE=1
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###
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### coreboot layout values
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###
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## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
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default CONFIG_ROM_IMAGE_SIZE = 65536
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default CONFIG_FALLBACK_SIZE = 131072
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##
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## Use a small 8K stack
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##
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default CONFIG_STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default CONFIG_HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
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default CONFIG_USE_OPTION_TABLE = 0
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default CONFIG_RAMBASE = 0x00004000
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default CONFIG_ROM_PAYLOAD = 1
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##
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## The default compiler
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##
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default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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#
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# CBFS
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#
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#
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default CONFIG_CBFS=0
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end
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