9df03a168f
Remove the mailbox call to notify the PSP that DRAM is ready. This is not supported on Family 17h. Remove the selectable SMU firmware. This is a feature of the PSP bootloader and the standard bootloader doesn't contain the ability. Clean up additional mentions of PSP within picasso. Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
139 lines
3.6 KiB
C
139 lines
3.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Intel Corp.
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/cpu.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/lapic.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/cpu.h>
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#include <soc/northbridge.h>
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#include <soc/smi.h>
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#include <soc/iomap.h>
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#include <console/console.h>
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/*
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* MP and SMM loading initialization.
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*/
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struct smm_relocation_attrs {
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uint32_t smbase;
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uint32_t tseg_base;
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uint32_t tseg_mask;
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};
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static struct smm_relocation_attrs relo_attrs;
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/*
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* Do essential initialization tasks before APs can be fired up -
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*
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* 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
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* creates the MTRR solution that the APs will use. Otherwise APs will try to
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* apply the incomplete solution as the BSP is calculating it.
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*/
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static void pre_mp_init(void)
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{
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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}
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static int get_cpu_count(void)
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{
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return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK)
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+ 1;
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}
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static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size)
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{
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void *smm_base;
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size_t smm_size;
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void *handler_base;
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size_t handler_size;
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/* Initialize global tracking state. */
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smm_region_info(&smm_base, &smm_size);
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smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
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relo_attrs.smbase = (uint32_t)smm_base;
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relo_attrs.tseg_base = relo_attrs.smbase;
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relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
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relo_attrs.tseg_mask |= SMM_TSEG_WB;
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*perm_smbase = (uintptr_t)handler_base;
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*perm_smsize = handler_size;
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*smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
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}
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static void relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase)
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{
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msr_t tseg_base, tseg_mask;
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amd64_smm_state_save_area_t *smm_state;
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tseg_base.lo = relo_attrs.tseg_base;
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tseg_base.hi = 0;
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wrmsr(SMM_ADDR_MSR, tseg_base);
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tseg_mask.lo = relo_attrs.tseg_mask;
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tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1);
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wrmsr(SMM_MASK_MSR, tseg_mask);
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smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase);
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smm_state->smbase = staggered_smbase;
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}
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = get_smm_info,
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.relocation_handler = relocation_handler,
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.post_mp_init = enable_smi_generation,
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};
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void picasso_init_cpus(struct device *dev)
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{
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/* Clear for take-off */
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if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
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printk(BIOS_ERR, "MP initialization failure.\n");
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/* The flash is now no longer cacheable. Reset to WP for performance. */
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mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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set_warm_reset_flag();
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}
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static void model_15_init(struct device *dev)
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{
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check_mca();
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setup_lapic();
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_15_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x670f00 },
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{ 0, 0 },
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};
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static const struct cpu_driver model_15 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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