9df60d36b2
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
87 lines
2.4 KiB
Plaintext
87 lines
2.4 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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/* TODO: Update for Glinda */
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Device(PCI0) {
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Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
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Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
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External(TOM1, IntObj) /* Generated by root_complex.c */
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Method(_BBN, 0, NotSerialized) {
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Return(0) /* Bus number = 0 */
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}
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Method(_STA, 0, NotSerialized) {
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Return(0x0B) /* Status is visible */
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}
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/* Operating System Capabilities Method */
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Method(_OSC, 4) {
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CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */
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/* Check for proper PCI/PCIe UUID */
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If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) {
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/* Let OS control everything */
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Return (Arg3)
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} Else {
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CDW1 |= 4 /* Unrecognized UUID */
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Return (Arg3)
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}
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}
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Name(CRES, ResourceTemplate() {
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, /* address granularity */
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0x0000, /* range minimum */
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0x00ff, /* range maximum */
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0x0000, /* translation */
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0x0100, /* length */
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,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
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IO(Decode16, 0x0cf8, 0x0cf8, 1, 8)
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WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, /* address granularity */
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0x0000, /* range minimum */
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0x0cf7, /* range maximum */
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0x0000, /* translation */
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0x0cf8 /* length */
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)
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WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, /* address granularity */
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0x0d00, /* range minimum */
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0xffff, /* range maximum */
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0x0000, /* translation */
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0xf300 /* length */
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)
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Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */
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Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
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/* memory space for PCI BARs below 4GB */
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Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
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})
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Method(_CRS, 0) {
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CreateDWordField(CRES, ^MMIO._BAS, MM1B)
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CreateDWordField(CRES, ^MMIO._LEN, MM1L)
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/* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
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MM1B = TOM1
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Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
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Local0 -= TOM1
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MM1L = Local0
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CreateWordField(CRES, ^PSB0._MAX, BMAX)
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CreateWordField(CRES, ^PSB0._LEN, BLEN)
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BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
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BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
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Return(CRES) /* note to change the Name buffer */
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} /* end of Method(_SB.PCI0._CRS) */
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/* 0:14.3 - LPC */
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#include <soc/amd/common/acpi/lpc.asl>
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} /* End PCI0 scope */
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