9e180387bd
chipset code (where it belongs) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
46 lines
1.3 KiB
C
46 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SOUTHBRIDGE_INTEL_I3100_I3100_H
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#define SOUTHBRIDGE_INTEL_I3100_I3100_H
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#include "chip.h"
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#define SATA_CMD 0x04
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#define SATA_PI 0x09
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#define SATA_PTIM 0x40
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#define SATA_STIM 0x42
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#define SATA_D1TIM 0x44
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#define SATA_SYNCC 0x48
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#define SATA_SYNCTIM 0x4A
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#define SATA_IIOC 0x54
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#define SATA_MAP 0x90
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#define SATA_PCS 0x91
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#define SATA_ACR0 0xA8
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#define SATA_ACR1 0xAC
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#define SATA_ATC 0xC0
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#define SATA_ATS 0xC4
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#define SATA_SP 0xD0
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#define SATA_MODE_IDE 0x00
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#define SATA_MODE_AHCI 0x01
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void i3100_enable(device_t dev);
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#endif
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