9f0266c599
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: I6ae22f9df4834508dfa304050fad44d45df45334 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
105 lines
2.4 KiB
C
105 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <commonlib/console/post_codes.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <device/mmio.h>
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#include <device/pci.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/systemagent.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/thermal.h>
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#include <intelpch/lockdown.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/systemagent.h>
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#include <spi-generic.h>
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#include "chip.h"
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#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
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#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
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#define CAM_CLK_EN (1 << 1)
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#define MIPI_CLK (1 << 0)
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#define HDPLL_CLK (0 << 0)
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static void pch_enable_isclk(void)
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{
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pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
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pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
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}
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static void pch_handle_sideband(config_t *config)
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{
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if (config->pch_isclk)
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pch_enable_isclk();
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}
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static void pch_finalize(void)
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{
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uint32_t reg32;
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uint8_t *pmcbase;
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config_t *config;
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tco_lockdown();
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/*
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* Set low maximum temp threshold value used for dynamic thermal sensor
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* shutdown consideration.
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*
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* If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
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* thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
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*/
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pch_thermal_configuration();
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config = config_of_soc();
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pmcbase = pmc_mmio_regs();
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if (config->s0ix_enable && config->cppmvric2_adsposcdis) {
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/* Enable Audio DSP OSC qualification for S0ix */
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reg32 = read32(pmcbase + CPPMVRIC2);
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reg32 &= ~ADSPOSCDIS;
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write32(pmcbase + CPPMVRIC2, reg32);
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}
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pch_handle_sideband(config);
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pmc_clear_pmcon_sts();
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/*
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* Lock chipset memory registers to protect SMM.
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* When SkipMpInit=0, this is done by FSP.
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*/
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if (!CONFIG(USE_INTEL_FSP_MP_INIT))
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cpu_lt_lock_memory();
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}
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static void sa_finalize(void)
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{
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if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
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sa_lock_pam();
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}
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static void soc_finalize(void *unused)
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{
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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pch_finalize();
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apm_control(APM_CNT_FINALIZE);
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sa_finalize();
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/* Indicate finalize step with post code */
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post_code(POST_OS_BOOT);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
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