9f1bd35b6d
Combination of several commits from Chromium tree: 3b875a2 [Lars: Update Memory ID for DVT board] b6d7c63 [Lili: Update Memory IDs] f203f99 [Lili: Add new SPD for Hynix H9CCNNN8GTALAR-NUD] a6571bf [Lili: Update Memory IDs] 80e1841 [Lili: Update Memory IDs] 58d4487 [Lili: Fix memory string show error in spd data] These commits bring lars' SPD data in line with the Chromium tree. Original-Change-Id: I54d0e6d2bbe86d5dc2ee5825f332d36abfa99084 Original-Change-Id: I9431393f369a1d2870bdabba1fc55d9cefae5c39 Original-Change-Id: I3b325a1801f49109429eb647d8d98a5537ce1b7b Original-Change-Id: Ie8a32d8a26ea1054e2df8432084a95d1cb03f991 Original-Change-Id: I64c73950e3bea57b6c5a90257211b3d6d7f1baab Original-Change-Id: I0e425fa4f0bae544680d5522c2e05a4f7a3be95a Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I7cc9b01012b0b9ed72804192bb5953243fc859b4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
121 lines
3.8 KiB
C
121 lines
3.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/byteorder.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <soc/pei_data.h>
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#include <soc/romstage.h>
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#include <string.h>
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#include "spd.h"
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static void mainboard_print_spd_info(uint8_t spd[])
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{
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const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
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const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
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const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
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const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
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const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
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const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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char spd_name[SPD_PART_LEN+1] = { 0 };
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int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
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int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
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int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
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int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
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int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
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int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
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int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
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/* Module type */
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printk(BIOS_INFO, "SPD: module type is ");
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switch (spd[SPD_DRAM_TYPE]) {
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case SPD_DRAM_DDR3:
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printk(BIOS_INFO, "DDR3\n");
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break;
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case SPD_DRAM_LPDDR3:
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printk(BIOS_INFO, "LPDDR3\n");
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break;
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default:
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printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
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break;
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}
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/* Module Part Number */
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memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
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spd_name[SPD_PART_LEN] = 0;
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printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
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printk(BIOS_INFO,
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"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
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banks, ranks, rows, cols, capmb);
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printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
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devw, busw);
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if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
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/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
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printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
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capmb / 8 * busw / devw * ranks);
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}
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}
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/* Copy SPD data for on-board memory */
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void mainboard_fill_spd_data(struct pei_data *pei_data)
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{
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char *spd_file;
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size_t spd_file_len;
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int spd_index, spd_span;
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spd_index = pei_data->mem_cfg_id;
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printk(BIOS_INFO, "SPD index %d\n", spd_index);
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/* Load SPD data from CBFS */
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spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
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&spd_file_len);
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if (!spd_file)
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die("SPD data not found.");
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/* make sure we have at least one SPD in the file. */
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if (spd_file_len < SPD_LEN)
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die("Missing SPD data.");
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/* Make sure we did not overrun the buffer */
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if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
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printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
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spd_index = 0;
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}
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/* Assume same memory in both channels */
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spd_span = spd_index * SPD_LEN;
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memcpy(pei_data->spd_data[0][0], spd_file + spd_span, SPD_LEN);
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if (spd_index != MEM_SINGLE_CHAN0 && spd_index != MEM_SINGLE_CHAN3
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&& spd_index != MEM_SINGLE_CHAN4 && spd_index != MEM_SINGLE_CHAN7
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&& spd_index != MEM_SINGLE_CHANB && spd_index != MEM_SINGLE_CHANC) {
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memcpy(pei_data->spd_data[1][0], spd_file + spd_span, SPD_LEN);
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printk(BIOS_INFO, "Dual channel SPD detected writing second channel\n");
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}
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/* Make sure a valid SPD was found */
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if (pei_data->spd_data[0][0][0] == 0)
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die("Invalid SPD data.");
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mainboard_print_spd_info(pei_data->spd_data[0][0]);
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}
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