9f91ced9dd
This patch renames X86_AMD_INIT_SIPI Kconfig to leverage the same logic (to skip 2nd SIPI and reduce delay between INIT and SIPI while perform AP initialization) even on newer Intel platform. Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
201 lines
4.4 KiB
Plaintext
201 lines
4.4 KiB
Plaintext
config PARALLEL_MP
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def_bool y
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depends on !LEGACY_SMP_INIT
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depends on SMP
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select CPU_INFO_V2
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help
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This option uses common MP infrastructure for bringing up APs
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in parallel. It additionally provides a more flexible mechanism
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for sequencing the steps of bringing up the APs.
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config PARALLEL_MP_AP_WORK
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def_bool n
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depends on PARALLEL_MP
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help
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Allow APs to do other work after initialization instead of going
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to sleep.
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config LEGACY_SMP_INIT
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bool
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choice LAPIC_ACCESS_MODE
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prompt "APIC operation mode"
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default XAPIC_ONLY
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config XAPIC_ONLY
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prompt "Set XAPIC mode"
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bool
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config X2APIC_ONLY
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prompt "Set X2APIC mode"
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bool
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depends on PARALLEL_MP
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config X2APIC_RUNTIME
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prompt "Support both XAPIC and X2APIC"
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bool
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depends on PARALLEL_MP
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endchoice
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config UDELAY_LAPIC
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bool
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default n
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config LAPIC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_LAPIC
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help
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Expose monotonic time using the local APIC.
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config UDELAY_LAPIC_FIXED_FSB
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int
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config UDELAY_TSC
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bool
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default n
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config UNKNOWN_TSC_RATE
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bool
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default y if LAPIC_MONOTONIC_TIMER
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config TSC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_TSC
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help
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Expose monotonic time using the TSC.
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config TSC_SYNC_LFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an lfence instruction in order to synchronize
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rdtsc. This is true for all modern AMD CPUs.
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config TSC_SYNC_MFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an mfence instruction in order to synchronize
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rdtsc. This is true for all modern Intel CPUs.
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config SETUP_XIP_CACHE
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bool
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depends on !NO_XIP_EARLY_STAGES
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help
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Select this option to set up an MTRR to cache XIP stages loaded
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from the bootblock. This is useful on platforms lacking a
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non-eviction mode and therefore need to be careful to avoid
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eviction.
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config LOGICAL_CPUS
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bool
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default y
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config HAVE_SMI_HANDLER
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bool
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default n
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depends on (SMM_ASEG || SMM_TSEG)
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config NO_SMM
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bool
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default n
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config SMM_ASEG
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bool
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default n
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depends on !NO_SMM
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config SMM_TSEG
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bool
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default y
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depends on !(NO_SMM || SMM_ASEG)
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if SMM_TSEG
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config SMM_MODULE_HEAP_SIZE
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hex
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default 0x4000
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help
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This option determines the size of the heap within the SMM handler
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modules.
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config SMM_MODULE_STACK_SIZE
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hex
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default 0x800 if ARCH_RAMSTAGE_X86_64
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default 0x400
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help
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This option determines the size of the stack within the SMM handler
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modules.
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config SMM_STUB_STACK_SIZE
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hex
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default 0x400
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help
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This option determines the size of the stack within the SMM handler
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modules.
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endif
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config SMM_LAPIC_REMAP_MITIGATION
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bool
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default y if NORTHBRIDGE_INTEL_I945
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default y if NORTHBRIDGE_INTEL_GM45
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default y if NORTHBRIDGE_INTEL_IRONLAKE
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default n
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config SERIALIZED_SMM_INITIALIZATION
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bool
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default n
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help
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On some CPUs, there is a race condition in SMM.
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This can occur when both hyperthreads change SMM state
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variables in parallel without coordination.
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Setting this option serializes the SMM initialization
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to avoid an ugly hang in the boot process at the cost
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of a slightly longer boot time.
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config X86_AMD_FIXED_MTRRS
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bool
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default n
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help
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This option informs the MTRR code to use the RdMem and WrMem fields
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in the fixed MTRR MSRs.
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config X86_INIT_NEED_1_SIPI
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bool
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default n
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help
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This option limits the number of SIPI signals sent during during the
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common AP setup. Intel documentation specifies an INIT SIPI SIPI
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sequence, however this doesn't work on some AMD and Intel platforms.
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These newer AMD and Intel platforms don't need the 10ms wait between
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INIT and SIPI, so skip that too to save some time.
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config SOC_SETS_MSRS
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bool
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default n
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help
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The SoC requires different access methods for reading and writing
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the MSRs. Use SoC specific routines to handle the MSR access.
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config RESERVE_MTRRS_FOR_OS
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bool
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default n
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help
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This option allows a platform to reserve 2 MTRRs for the OS usage.
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The Intel SDM documents that the the first 6 MTRRs are intended for
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the system BIOS and the last 2 are to be reserved for OS usage.
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However, modern OSes use PAT to control cacheability instead of
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using MTRRs.
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config CPU_INFO_V2
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bool
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depends on PARALLEL_MP
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help
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Enables the new method of locating struct cpu_info. This new method
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uses the %gs segment to locate the cpu_info pointer. The old method
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relied on the stack being CONFIG_STACK_SIZE aligned.
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