This patch introduces a config option for SoC code to choose the applicable SoC workaround. For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE` to apply UFS OCP timeout disable workaround. At present ADL SoC only selects so, and in future MTL and others should check with Intel prior selecting this kconfig. It's the placeholder to add more workaround in required going forward. BUG=none TEST=Able to build and boot Google/Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68309 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
486 lines
13 KiB
Plaintext
486 lines
13 KiB
Plaintext
config SOC_INTEL_ALDERLAKE
|
|
bool
|
|
help
|
|
Intel Alderlake support. Mainboards should specify the PCH
|
|
type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead
|
|
of selecting this option directly.
|
|
|
|
config SOC_INTEL_RAPTORLAKE
|
|
bool
|
|
help
|
|
Intel Raptorlake support. Mainboards using RPL should select
|
|
SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together.
|
|
|
|
config SOC_INTEL_ALDERLAKE_PCH_M
|
|
bool
|
|
select SOC_INTEL_ALDERLAKE
|
|
help
|
|
Choose this option if your mainboard has a PCH-M chipset.
|
|
|
|
config SOC_INTEL_ALDERLAKE_PCH_N
|
|
bool
|
|
select SOC_INTEL_ALDERLAKE
|
|
select MICROCODE_BLOB_UNDISCLOSED
|
|
help
|
|
Choose this option if your mainboard has a PCH-N chipset.
|
|
|
|
config SOC_INTEL_ALDERLAKE_PCH_P
|
|
bool
|
|
select SOC_INTEL_ALDERLAKE
|
|
select HAVE_INTEL_FSP_REPO
|
|
select PLATFORM_USES_FSP2_3
|
|
help
|
|
Choose this option if your mainboard has a PCH-P chipset.
|
|
|
|
config SOC_INTEL_ALDERLAKE_PCH_S
|
|
bool
|
|
select SOC_INTEL_ALDERLAKE
|
|
select HAVE_INTEL_FSP_REPO
|
|
select PLATFORM_USES_FSP2_3
|
|
help
|
|
Choose this option if your mainboard has a PCH-S chipset.
|
|
|
|
if SOC_INTEL_ALDERLAKE
|
|
|
|
config CPU_SPECIFIC_OPTIONS
|
|
def_bool y
|
|
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
|
|
select ACPI_ADL_IPU_ES_SUPPORT
|
|
select ARCH_X86
|
|
select BOOT_DEVICE_SUPPORTS_WRITES
|
|
select CACHE_MRC_SETTINGS
|
|
select CPU_INTEL_COMMON
|
|
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
|
|
select CPU_SUPPORTS_INTEL_TME
|
|
select CPU_SUPPORTS_PM_TIMER_EMULATION
|
|
select DISPLAY_FSP_VERSION_INFO
|
|
select DRIVERS_USB_ACPI
|
|
select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
|
|
select FSP_COMPRESS_FSP_S_LZ4
|
|
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
|
|
select FSP_M_XIP
|
|
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
|
|
select FSP_USES_CB_DEBUG_EVENT_HANDLER
|
|
select FSPS_HAS_ARCH_UPD
|
|
select GENERIC_GPIO_LIB
|
|
select HAVE_DEBUG_RAM_SETUP
|
|
select HAVE_FSP_GOP
|
|
select HAVE_HYPERTHREADING
|
|
select INTEL_DESCRIPTOR_MODE_CAPABLE
|
|
select HAVE_SMI_HANDLER
|
|
select IDT_IN_EVERY_STAGE
|
|
select INTEL_GMA_ACPI
|
|
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
|
|
select INTEL_GMA_OPREGION_2_1
|
|
select MRC_SETTINGS_PROTECT
|
|
select PARALLEL_MP_AP_WORK
|
|
select PLATFORM_USES_FSP2_2
|
|
select PMC_GLOBAL_RESET_ENABLE_LOCK
|
|
select SOC_INTEL_COMMON
|
|
select CPU_INTEL_COMMON_VOLTAGE
|
|
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
|
|
select SOC_INTEL_COMMON_BLOCK
|
|
select SOC_INTEL_COMMON_BLOCK_ACPI
|
|
select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
|
|
select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
|
|
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
|
|
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
|
|
select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
|
|
select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
|
|
select SOC_INTEL_COMMON_BLOCK_CAR
|
|
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
|
|
select SOC_INTEL_COMMON_BLOCK_CNVI
|
|
select SOC_INTEL_COMMON_BLOCK_CPU
|
|
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
|
|
select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
|
|
select SOC_INTEL_COMMON_BLOCK_DTT
|
|
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
|
|
select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI
|
|
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
|
|
select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N
|
|
select SOC_INTEL_COMMON_BLOCK_HDA
|
|
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
|
|
select SOC_INTEL_COMMON_BLOCK_IPU if !SOC_INTEL_ALDERLAKE_PCH_S
|
|
select SOC_INTEL_COMMON_BLOCK_IRQ
|
|
select SOC_INTEL_COMMON_BLOCK_MEMINIT
|
|
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
|
|
select SOC_INTEL_COMMON_BLOCK_PMC_EPOC
|
|
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
|
|
select SOC_INTEL_COMMON_BLOCK_SA
|
|
select SOC_INTEL_COMMON_BLOCK_SMM
|
|
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
|
|
select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
|
|
select SOC_INTEL_COMMON_BLOCK_XHCI
|
|
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
|
|
select SOC_INTEL_COMMON_BASECODE
|
|
select SOC_INTEL_COMMON_FSP_RESET
|
|
select SOC_INTEL_COMMON_PCH_CLIENT
|
|
select SOC_INTEL_COMMON_RESET
|
|
select SOC_INTEL_CSE_SEND_EOP_EARLY
|
|
select SOC_INTEL_CSE_SET_EOP
|
|
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
|
|
select HAVE_INTEL_COMPLIANCE_TEST_MODE
|
|
select SSE2
|
|
select SUPPORT_CPU_UCODE_IN_CBFS
|
|
select TSC_MONOTONIC_TIMER
|
|
select UDELAY_TSC
|
|
select UDK_202005_BINDING
|
|
select VBOOT_LIB
|
|
|
|
config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT
|
|
bool
|
|
default y if !SOC_INTEL_ALDERLAKE_PCH_S
|
|
default n if SOC_INTEL_ALDERLAKE_PCH_S
|
|
select SOC_INTEL_COMMON_BLOCK_TCSS
|
|
select SOC_INTEL_COMMON_BLOCK_USB4
|
|
select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
|
|
select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
|
|
|
|
config ALDERLAKE_CONFIGURE_DESCRIPTOR
|
|
bool
|
|
help
|
|
Select this if the descriptor needs to be updated at runtime. This
|
|
can only be done if the descriptor region is writable, and should only
|
|
be used as a temporary workaround.
|
|
|
|
config ALDERLAKE_CAR_ENHANCED_NEM
|
|
bool
|
|
default y if !INTEL_CAR_NEM
|
|
select INTEL_CAR_NEM_ENHANCED
|
|
select CAR_HAS_SF_MASKS
|
|
select COS_MAPPED_TO_MSB
|
|
select CAR_HAS_L3_PROTECTED_WAYS
|
|
|
|
config MAX_CPUS
|
|
int
|
|
default 24
|
|
|
|
config DCACHE_RAM_BASE
|
|
default 0xfef00000
|
|
|
|
config DCACHE_RAM_SIZE
|
|
default 0xc0000
|
|
help
|
|
The size of the cache-as-ram region required during bootblock
|
|
and/or romstage.
|
|
|
|
config DCACHE_BSP_STACK_SIZE
|
|
hex
|
|
default 0x80400
|
|
help
|
|
The amount of anticipated stack usage in CAR by bootblock and
|
|
other stages. In the case of FSP_USES_CB_STACK default value will be
|
|
sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
|
|
(~1KiB).
|
|
|
|
config FSP_TEMP_RAM_SIZE
|
|
hex
|
|
default 0x20000
|
|
help
|
|
The amount of anticipated heap usage in CAR by FSP.
|
|
Refer to Platform FSP integration guide document to know
|
|
the exact FSP requirement for Heap setup.
|
|
|
|
config CHIPSET_DEVICETREE
|
|
string
|
|
default "soc/intel/alderlake/chipset_pch_s.cb" if SOC_INTEL_ALDERLAKE_PCH_S
|
|
default "soc/intel/alderlake/chipset.cb"
|
|
|
|
config EXT_BIOS_WIN_BASE
|
|
default 0xf8000000
|
|
|
|
config EXT_BIOS_WIN_SIZE
|
|
default 0x2000000
|
|
|
|
config IFD_CHIPSET
|
|
string
|
|
default "adl"
|
|
|
|
config IED_REGION_SIZE
|
|
hex
|
|
default 0x400000
|
|
|
|
config HEAP_SIZE
|
|
hex
|
|
default 0x10000
|
|
|
|
# Intel recommends reserving the following resources per PCIe TBT root port,
|
|
# from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5
|
|
# - 42 buses
|
|
# - 194 MiB Non-prefetchable memory
|
|
# - 448 MiB Prefetchable memory
|
|
if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
|
|
|
|
config PCIEXP_HOTPLUG_BUSES
|
|
int
|
|
default 42
|
|
|
|
config PCIEXP_HOTPLUG_MEM
|
|
hex
|
|
default 0xc200000
|
|
|
|
config PCIEXP_HOTPLUG_PREFETCH_MEM
|
|
hex
|
|
default 0x1c000000
|
|
|
|
endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
|
|
|
|
config MAX_PCH_ROOT_PORTS
|
|
int
|
|
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
|
|
default 12 if SOC_INTEL_ALDERLAKE_PCH_N
|
|
default 12 if SOC_INTEL_ALDERLAKE_PCH_P
|
|
default 28 if SOC_INTEL_ALDERLAKE_PCH_S
|
|
|
|
config MAX_CPU_ROOT_PORTS
|
|
int
|
|
default 1 if SOC_INTEL_ALDERLAKE_PCH_M
|
|
default 0 if SOC_INTEL_ALDERLAKE_PCH_N
|
|
default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S
|
|
|
|
config MAX_TBT_ROOT_PORTS
|
|
int
|
|
default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S
|
|
default 2 if SOC_INTEL_ALDERLAKE_PCH_M
|
|
default 4 if SOC_INTEL_ALDERLAKE_PCH_P
|
|
|
|
config MAX_ROOT_PORTS
|
|
int
|
|
default MAX_PCH_ROOT_PORTS
|
|
|
|
config MAX_PCIE_CLOCK_SRC
|
|
int
|
|
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
|
|
default 5 if SOC_INTEL_ALDERLAKE_PCH_N
|
|
default 18 if SOC_INTEL_ALDERLAKE_PCH_S
|
|
default 10 if SOC_INTEL_ALDERLAKE_PCH_P
|
|
help
|
|
With external clock buffer, Alderlake-P can support up to three additional source clocks.
|
|
This is done by setting the corresponding GPIO pin(s) to native function to use as
|
|
SRCCLK_OE[6..9]. In addition, SRCCLK6 does not need to be set to free running clock.
|
|
If any of SRCCLKReq 6..9 is asserted, SRCCLK6 will be turned on.
|
|
|
|
config MAX_PCIE_CLOCK_REQ
|
|
int
|
|
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
|
|
default 5 if SOC_INTEL_ALDERLAKE_PCH_N
|
|
default 10 if SOC_INTEL_ALDERLAKE_PCH_P
|
|
default 18 if SOC_INTEL_ALDERLAKE_PCH_S
|
|
|
|
config SMM_TSEG_SIZE
|
|
hex
|
|
default 0x800000
|
|
|
|
config SMM_RESERVED_SIZE
|
|
hex
|
|
default 0x200000
|
|
|
|
config PCR_BASE_ADDRESS
|
|
hex
|
|
default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S
|
|
default 0xfd000000
|
|
help
|
|
This option allows you to select MMIO Base Address of sideband bus.
|
|
|
|
config ECAM_MMCONF_BASE_ADDRESS
|
|
default 0xc0000000
|
|
|
|
config CPU_BCLK_MHZ
|
|
int
|
|
default 100
|
|
|
|
config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
|
|
int
|
|
default 120
|
|
|
|
config CPU_XTAL_HZ
|
|
default 38400000
|
|
|
|
config SOC_INTEL_UFS_CLK_FREQ_HZ
|
|
int
|
|
default 19200000
|
|
|
|
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
|
|
int
|
|
default 133
|
|
|
|
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
|
|
int
|
|
default 7
|
|
|
|
config SOC_INTEL_I2C_DEV_MAX
|
|
int
|
|
default 8
|
|
|
|
config SOC_INTEL_ALDERLAKE_S3
|
|
bool
|
|
default n
|
|
help
|
|
Select if using S3 instead of S0ix to disable D3Cold.
|
|
|
|
config ENABLE_SATA_TEST_MODE
|
|
bool "Enable test mode for SATA margining"
|
|
default n
|
|
help
|
|
Enable SATA test mode in FSP-S.
|
|
|
|
config SOC_INTEL_UART_DEV_MAX
|
|
int
|
|
default 7
|
|
|
|
config CONSOLE_UART_BASE_ADDRESS
|
|
hex
|
|
default 0xfe03e000
|
|
depends on INTEL_LPSS_UART_FOR_CONSOLE
|
|
|
|
config VBT_DATA_SIZE_KB
|
|
int
|
|
default 9
|
|
|
|
# Clock divider parameters for 115200 baud rate
|
|
# Baudrate = (UART source clock * M) /(N *16)
|
|
# ADL UART source clock: 100MHz
|
|
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
|
|
hex
|
|
default 0x25a
|
|
|
|
config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
|
|
hex
|
|
default 0x7fff
|
|
|
|
config VBOOT
|
|
select VBOOT_MUST_REQUEST_DISPLAY
|
|
select VBOOT_STARTS_IN_BOOTBLOCK
|
|
select VBOOT_VBNV_CMOS
|
|
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
|
|
select VBOOT_X86_SHA256_ACCELERATION
|
|
|
|
# Default hash block size is 1KiB. Increasing it to 4KiB to improve
|
|
# hashing time as well as read time. This helps in improving
|
|
# boot time for Alder Lake.
|
|
config VBOOT_HASH_BLOCK_SIZE
|
|
hex
|
|
default 0x1000
|
|
|
|
config CBFS_SIZE
|
|
default 0x200000
|
|
|
|
config PRERAM_CBMEM_CONSOLE_SIZE
|
|
hex
|
|
default 0x2000
|
|
|
|
config FSP_TYPE_IOT
|
|
bool
|
|
default n
|
|
help
|
|
This option allows to select FSP IOT type from 3rdparty/fsp repo
|
|
|
|
config FSP_HEADER_PATH
|
|
string "Location of FSP headers"
|
|
default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N
|
|
default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE
|
|
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT
|
|
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT
|
|
default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P
|
|
default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S
|
|
default "src/vendorcode/intel/fsp/fsp2_0/alderlake/"
|
|
|
|
config FSP_FD_PATH
|
|
string
|
|
depends on FSP_USE_REPO
|
|
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT
|
|
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT
|
|
default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P
|
|
default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S
|
|
|
|
config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
|
|
int "Debug Consent for ADL"
|
|
# USB DBC is more common for developers so make this default to 2 if
|
|
# SOC_INTEL_DEBUG_CONSENT=y
|
|
default 2 if SOC_INTEL_DEBUG_CONSENT
|
|
default 0
|
|
help
|
|
This is to control debug interface on SOC.
|
|
Setting non-zero value will allow to use DBC or DCI to debug SOC.
|
|
PlatformDebugConsent in FspmUpd.h has the details.
|
|
|
|
Desired platform debug type are
|
|
0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power),
|
|
7:Manual
|
|
|
|
config DATA_BUS_WIDTH
|
|
int
|
|
default 128
|
|
|
|
config DIMMS_PER_CHANNEL
|
|
int
|
|
default 2
|
|
|
|
config MRC_CHANNEL_WIDTH
|
|
int
|
|
default 16
|
|
|
|
config ACPI_ADL_IPU_ES_SUPPORT
|
|
def_bool n
|
|
help
|
|
Enables ACPI entry to provide silicon type information to IPU kernel driver.
|
|
|
|
config ALDERLAKE_ENABLE_SOC_WORKAROUND
|
|
bool
|
|
default y
|
|
select SOC_INTEL_UFS_OCP_TIMER_DISABLE
|
|
help
|
|
Selects the workarounds applicable for Alder Lake SoC.
|
|
|
|
choice
|
|
prompt "Multiprocessor (MP) Initialization configuration to use"
|
|
default USE_FSP_MP_INIT
|
|
|
|
config USE_FSP_MP_INIT
|
|
bool "Use FSP MP init"
|
|
select MP_SERVICES_PPI_V2
|
|
help
|
|
Upon selection, coreboot brings APs from reset and the FSP runs feature programming.
|
|
|
|
config USE_COREBOOT_MP_INIT
|
|
bool "Use coreboot MP init"
|
|
# FSP assumes ownership of the APs (Application Processors)
|
|
# upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD.
|
|
# Hence, select `MP_SERVICES_PPI_V2_NOOP` config to pass a valid
|
|
# pointer to the CpuMpPpi UPD with FSP_UNSUPPORTED type APIs.
|
|
# This will protect APs from getting hijacked by FSP while coreboot
|
|
# decides to set SkipMpInit UPD.
|
|
select MP_SERVICES_PPI_V2_NOOP
|
|
select RELOAD_MICROCODE_PATCH
|
|
help
|
|
Upon selection, coreboot performs MP Init.
|
|
|
|
endchoice
|
|
|
|
if STITCH_ME_BIN
|
|
|
|
config CSE_BPDT_VERSION
|
|
default "1.7"
|
|
|
|
endif
|
|
|
|
config SI_DESC_REGION
|
|
string "Descriptor Region name"
|
|
default "SI_DESC"
|
|
help
|
|
Name of Descriptor Region in the FMAP
|
|
|
|
config SI_DESC_REGION_SZ
|
|
int
|
|
default 4096
|
|
help
|
|
Size of Descriptor Region in the FMAP
|
|
|
|
config BUILDING_WITH_DEBUG_FSP
|
|
bool "Debug FSP is used for the build"
|
|
default n
|
|
help
|
|
Set this option if debug build of FSP is used.
|
|
|
|
endif
|