a0368a0950
This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable. User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated UPD. Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig to make HECI disable and WHL/CML has to rely on FSP to make HECI disable. Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
135 lines
3.6 KiB
C
135 lines
3.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/p2sb.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/smihandler.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include "chip.h"
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#define CSME0_FBE 0xf
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#define CSME0_BAR 0x0
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#define CSME0_FID 0xb0
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const struct smm_save_state_ops *get_smm_save_state_ops(void)
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{
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return &em64t101_smm_ops;
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}
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static void pch_disable_heci(void)
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{
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struct pcr_sbi_msg msg = {
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.pid = PID_CSME0,
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.offset = 0,
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.opcode = PCR_WRITE,
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.is_posted = false,
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.fast_byte_enable = CSME0_FBE,
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.bar = CSME0_BAR,
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.fid = CSME0_FID
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};
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/* Bit 0: Set to make HECI#1 Function disable */
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uint32_t data32 = 1;
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uint8_t response;
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int status;
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/* unhide p2sb device */
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p2sb_unhide();
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/* Send SBI command to make HECI#1 function disable */
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status = pcr_execute_sideband_msg(&msg, &data32, &response);
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if (status && response)
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printk(BIOS_ERR, "Fail to make CSME function disable\n");
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/* Ensure to Lock SBI interface after this command */
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p2sb_disable_sideband_access();
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/* hide p2sb device */
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p2sb_hide();
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}
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/*
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* Specific SOC SMI handler during ramstage finalize phase
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*
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* BIOS can't make CSME function disable as is due to POSTBOOT_SAI
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* restriction in place from ICP chipset. Hence create SMI Handler to
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* perform CSME function disabling logic during SMM mode.
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*/
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void smihandler_soc_at_finalize(void)
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{
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const struct soc_intel_icelake_config *config;
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const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE);
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if (!dev || !dev->chip_info) {
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printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
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__func__);
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return;
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}
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config = dev->chip_info;
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if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
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pch_disable_heci();
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}
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void smihandler_soc_check_illegal_access(uint32_t tco_sts)
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{
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if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
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&& fast_spi_wpd_status()))
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return;
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/*
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* BWE is RW, so the SMI was caused by a
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* write to BWE, not by a write to the BIOS
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*
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* This is the place where we notice someone
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* is trying to tinker with the BIOS. We are
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* trying to be nice and just ignore it. A more
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* resolute answer would be to power down the
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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fast_spi_enable_wp();
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}
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/* SMI handlers that should be serviced in SCI mode too. */
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uint32_t smihandler_soc_get_sci_mask(void)
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{
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uint32_t sci_mask =
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SMI_HANDLER_SCI_EN(APM_STS_BIT) |
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SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
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return sci_mask;
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}
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const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
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[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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[APM_STS_BIT] = smihandler_southbridge_apmc,
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[PM1_STS_BIT] = smihandler_southbridge_pm1,
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[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
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[GPIO_STS_BIT] = smihandler_southbridge_gpi,
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[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
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[MCSMI_STS_BIT] = smihandler_southbridge_mc,
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[TCO_STS_BIT] = smihandler_southbridge_tco,
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[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
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[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
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};
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