a0720431b4
Shift is done in multiples of 8 (1 << 3) bits. It was fixed already for i82801ix/jx. Change-Id: I5e1c2b3bf4ba68f34eb43e59fe783d5cd6e0a39a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
136 lines
3.3 KiB
C
136 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <types.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/em64t101_save_state.h>
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#include <cpu/intel/model_2065x/model_2065x.h>
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#include <southbridge/intel/common/finalize.h>
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#include <southbridge/intel/common/pmbase.h>
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#include <southbridge/intel/ibexpeak/me.h>
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#include "pch.h"
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/* We are using PCIe accesses for now
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* 1. the chipset can do it
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* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
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*/
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#include <northbridge/intel/ironlake/ironlake.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/common/pmutil.h>
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static void southbridge_gate_memory_reset_real(int offset,
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u16 use, u16 io, u16 lvl)
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{
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u32 reg32;
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/* Make sure it is set as GPIO */
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reg32 = inl(use);
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if (!(reg32 & (1 << offset))) {
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reg32 |= (1 << offset);
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outl(reg32, use);
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}
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/* Make sure it is set as output */
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reg32 = inl(io);
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if (reg32 & (1 << offset)) {
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reg32 &= ~(1 << offset);
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outl(reg32, io);
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}
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/* Drive the output low */
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reg32 = inl(lvl);
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reg32 &= ~(1 << offset);
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outl(reg32, lvl);
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}
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/*
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* Drive GPIO 60 low to gate memory reset in S3.
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*
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* Intel reference designs all use GPIO 60 but it is
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* not a requirement and boards could use a different pin.
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*/
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void southbridge_gate_memory_reset(void)
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{
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u16 gpiobase;
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gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
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if (!gpiobase)
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return;
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if (CONFIG_DRAM_RESET_GATE_GPIO >= 32)
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southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32,
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gpiobase + GPIO_USE_SEL2,
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gpiobase + GP_IO_SEL2,
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gpiobase + GP_LVL2);
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else
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southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO,
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gpiobase + GPIO_USE_SEL,
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gpiobase + GP_IO_SEL,
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gpiobase + GP_LVL);
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}
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void southbridge_smi_monitor(void)
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{
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#define IOTRAP(x) (trap_sts & (1 << x))
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u32 trap_sts, trap_cycle;
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u32 data, mask = 0;
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int i;
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trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
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RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
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trap_cycle = RCBA32(0x1e10);
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for (i = 16; i < 20; i++) {
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if (trap_cycle & (1 << i))
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mask |= (0xff << ((i - 16) << 3));
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}
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/* IOTRAP(3) SMI function call */
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if (IOTRAP(3)) {
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return;
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}
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/* IOTRAP(2) currently unused
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* IOTRAP(1) currently unused */
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/* IOTRAP(0) SMIC */
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if (IOTRAP(0)) {
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if (!(trap_cycle & (1 << 24))) { // It's a write
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printk(BIOS_DEBUG, "SMI1 command\n");
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data = RCBA32(0x1e18);
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data &= mask;
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// if (smi1)
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// southbridge_smi_command(data);
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// return;
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}
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// Fall through to debug
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}
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printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
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for (i = 0; i < 4; i++) {
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if (IOTRAP(i))
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printk(BIOS_DEBUG, " TRAP = %d\n", i);
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}
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printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
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printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
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printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
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if (!(trap_cycle & (1 << 24))) {
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/* Write Cycle */
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data = RCBA32(0x1e18);
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printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
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}
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#undef IOTRAP
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}
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void southbridge_finalize_all(void)
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{
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/* TODO: Finalize ME */
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intel_pch_finalize_smm();
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intel_ironlake_finalize_smm();
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intel_model_2065x_finalize_smm();
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}
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