Files
system76-coreboot/src/mainboard/intel/archercity_crb/util.c
Shuo Liu a0aff6e159 soc/intel/xeon_sp: Add get_cxl_mode
Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.

Add get_cxl_mode so that SoC codes do not need to get this
configuration from VPD any more.

TEST=Build and boot on intel/archercity CRB with no significant log
differences

Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-02 17:43:42 +00:00

21 lines
425 B
C

/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/ocp/include/vpd.h>
#include <soc/chip_common.h>
#include <soc/util.h>
#if CONFIG(SOC_INTEL_HAS_CXL)
enum xeonsp_cxl_mode get_cxl_mode(void)
{
int ocp_cxl_mode = get_cxl_mode_from_vpd();
switch (ocp_cxl_mode) {
case CXL_SYSTEM_MEMORY:
return XEONSP_CXL_SYS_MEM;
case CXL_SPM:
return XEONSP_CXL_SP_MEM;
default:
return XEONSP_CXL_DISABLED;
}
}
#endif