a0d9ad322f
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
96 lines
2.4 KiB
Plaintext
96 lines
2.4 KiB
Plaintext
config BOARD_INTEL_KBLRVP_COMMON
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def_bool n
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select BOARD_ROMSIZE_KB_16384
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select EC_ACPI
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_SPD_IN_CBFS
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select SOC_INTEL_KABYLAKE
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config BOARD_INTEL_KBLRVP3
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select BOARD_INTEL_KBLRVP_COMMON
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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config BOARD_INTEL_KBLRVP7
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select BOARD_INTEL_KBLRVP_COMMON
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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config BOARD_INTEL_KBLRVP8
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select BOARD_INTEL_KBLRVP_COMMON
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select MAINBOARD_USES_IFD_GBE_REGION
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select SKYLAKE_SOC_PCH_H
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config BOARD_INTEL_KBLRVP11
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select BOARD_INTEL_KBLRVP_COMMON
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SKYLAKE_SOC_PCH_H
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if BOARD_INTEL_KBLRVP_COMMON
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config DISABLE_HECI1_AT_PRE_BOOT
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default y
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config VBOOT
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select VBOOT_LID_SWITCH
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config MAINBOARD_DIR
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default "intel/kblrvp"
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config VARIANT_DIR
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default "rvp3" if BOARD_INTEL_KBLRVP3
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default "rvp7" if BOARD_INTEL_KBLRVP7
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default "rvp8" if BOARD_INTEL_KBLRVP8
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default "rvp11" if BOARD_INTEL_KBLRVP11
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config MAINBOARD_PART_NUMBER
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default "Kblrvp"
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config MAINBOARD_FAMILY
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string
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default "Intel_Kblrvp"
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config TPM_PIRQ
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hex
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default 0x18 # GPP_E0_IRQ
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config DEVICETREE
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default "variants/baseboard/devicetree.cb"
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config IFD_BIN_PATH
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string
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depends on HAVE_IFD_BIN
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default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/descriptor.rvp3.bin" if BOARD_INTEL_KBLRVP3
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default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/descriptor.rvp7.bin" if BOARD_INTEL_KBLRVP7
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default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/descriptor.rvp8.bin" if BOARD_INTEL_KBLRVP8
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config ME_BIN_PATH
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string
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depends on HAVE_ME_BIN
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default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/me.rvp3.bin" if BOARD_INTEL_KBLRVP3
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default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/me.rvp7.bin" if BOARD_INTEL_KBLRVP7
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default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/me.rvp8.bin" if BOARD_INTEL_KBLRVP8
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0xd00
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config DIMM_SPD_SIZE
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default 512 if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 #DDR4
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config UART_FOR_CONSOLE
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int
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default 2
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config USE_PM_ACPI_TIMER
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default n if BOARD_INTEL_KBLRVP3
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default n if BOARD_INTEL_KBLRVP7
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endif
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