system76-coreboot

Files

Jamie Ryu 12367e0db1 mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts

This patch adds initial romstage code and spd data for DDR5 memory
parts for MTL-RVP. This also configures memory based on the board id.

Memory - x32 DDR5 SBS SODIMM 1DPC
Vendor/Model - SK-Hynix/HMCG66MEBSA092N

BUG=b:224325352
TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

2023-01-10 14:42:37 +00:00

acpi

tree/acpi: Replace constant "Zero" with actual number

2022-12-27 09:06:47 +00:00

arch

arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields

2023-01-08 01:27:14 +00:00

commonlib

vc/google: Add and use POST_CODE_CLEAR definition

2023-01-07 03:31:41 +00:00

console

lib: Hook up libhwbase in romstage