a1843d8411
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and set the FSP option for PM ACPI timer enablement from its value instead of using the old devicetree option. Also drop the obsolete devicetree option from soc code and from the mainboards and add a corresponding Kconfig entry instead. Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
282 lines
9.1 KiB
Plaintext
282 lines
9.1 KiB
Plaintext
chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_WAKE_PIN"
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register "eist_enable" = "1"
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# Set the Thermal Control Circuit (TCC) activation value to 95C
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# even though FSP integration guide says to set it to 100C for SKL-U
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# (offset at 0), because when the TCC activates at 100C, the CPU
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# will have already shut itself down from overheating protection.
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register "tcc_offset" = "5" # TCC of 95C
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_C"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f
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register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef
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register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff
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register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f
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# Disable DPTF
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register "dptf_enable" = "0"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsEnable[2]" = "1"
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[1]" = "0"
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register "SataPortsDevSlp[2]" = "0"
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register "SataSpeedLimit" = "2"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "0"
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register "SsicPortEnable" = "0"
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register "ScsEmmcHs400Enabled" = "0"
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register "SkipExtGfxScan" = "1"
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register "HeciEnabled" = "1"
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register "SaGv" = "SaGv_Enabled"
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "1" # 1s
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register "PmConfigSlpSusMinAssert" = "3" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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# VR Settings Configuration for 4 Domains
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#+----------------+-------+-------+-------------+-------+
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#| Domain/Setting | SA | IA | GT-Unsliced | GT |
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#+----------------+-------+-------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.voltage_limit = 1520,
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}"
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register "PcieRpEnable[2]" = "1"
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register "PcieRpEnable[3]" = "1"
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register "PcieRpEnable[4]" = "1"
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register "PcieRpEnable[8]" = "1"
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register "PcieRpEnable[9]" = "1"
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register "PcieRpEnable[10]" = "1"
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register "PcieRpEnable[11]" = "1"
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register "PcieRpClkSrcNumber[0]" = "0"
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register "PcieRpClkSrcNumber[3]" = "1"
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register "PcieRpClkSrcNumber[4]" = "2"
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register "PcieRpClkSrcNumber[8]" = "3"
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register "PcieRpClkSrcNumber[9]" = "3"
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register "PcieRpClkSrcNumber[10]" = "3"
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register "PcieRpClkSrcNumber[11]" = "3"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right)
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right)
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # WiFi
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left)
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left)
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # GL850G for F_USB1 and F_USB2 headers
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header
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# PL2 override 25W
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register "power_limits_config" = "{
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.tdp_pl2_override = 25,
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}"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on end # SA thermal subsystem
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device pci 14.0 on end # USB xHCI
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device pci 14.1 on end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 14.3 off end # Camera
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on end # SATA
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 on end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 on # PCI Express Port 5
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smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
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"SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X"
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end
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device pci 1c.5 on end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on # PCI Express Port 9
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
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"SSD_M.2 2242/2280" "SlotDataBusWidth4X"
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end
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device pci 1d.1 on end # PCI Express Port 10
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device pci 1d.2 on end # PCI Express Port 11
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device pci 1d.3 on end # PCI Express Port 12
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device pci 1e.6 off end # SDXC
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip superio/ite/it8786e
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register "TMPIN1.mode" = "THERMAL_PECI"
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register "TMPIN1.offset" = "100"
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register "TMPIN1.min" = "128"
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register "TMPIN2.mode" = "THERMAL_RESISTOR"
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register "TMPIN2.min" = "128"
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register "TMPIN3.mode" = "THERMAL_MODE_DISABLED"
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register "ec.vin_mask" = "VIN_ALL"
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# FAN1 is CPU fan (on board)
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register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
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register "FAN1.smart.tmpin" = " 1"
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register "FAN1.smart.tmp_off" = "35"
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register "FAN1.smart.tmp_start" = "60"
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register "FAN1.smart.tmp_full" = "85"
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register "FAN1.smart.tmp_delta" = " 2"
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register "FAN1.smart.pwm_start" = "20"
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register "FAN1.smart.slope" = "24"
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# FAN2 is system fan (4 pin connector populated)
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#register "FAN2.mode" = "FAN_MODE_OFF"
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# FAN3 PWM is used for LVDS backlight control
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#register "FAN3.mode" = "FAN_MODE_OFF"
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device pnp 2e.1 on # COM 1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 on # COM 2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Printer Port
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io 0x60 = 0x378
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io 0x62 = 0x778
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irq 0x70 = 5
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drq 0x74 = 3
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end
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device pnp 2e.4 on # Environment Controller
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io 0x60 = 0xa40
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io 0x62 = 0xa30
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irq 0x70 = 9
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # Mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 off # GPIO
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end
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device pnp 2e.8 on # COM 3
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io 0x60 = 0x3e8
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irq 0x70 = 3
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end
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device pnp 2e.9 on # COM 4
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io 0x60 = 0x2e8
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irq 0x70 = 4
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end
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device pnp 2e.a off end # CIR
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device pnp 2e.b on # COM 5
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io 0x60 = 0x2f0
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irq 0x70 = 3
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end
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device pnp 2e.c on # COM 6
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io 0x60 = 0x2e0
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irq 0x70 = 4
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end
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end
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end # LPC Interface
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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