a19bc34430
This makes it easier to have common code for MP init on AMD systems. Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
95 lines
2.5 KiB
C
95 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <amdblocks/cpu.h>
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#include <amdblocks/mca.h>
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#include <amdblocks/reset.h>
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#include <amdblocks/smm.h>
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#include <assert.h>
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#include <console/console.h>
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#include <cpu/amd/microcode.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/smi.h>
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#include <types.h>
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_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
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"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
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/* MP and SMM loading initialization. */
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/*
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* Do essential initialization tasks before APs can be fired up -
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*
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* 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
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* creates the MTRR solution that the APs will use. Otherwise APs will try to
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* apply the incomplete solution as the BSP is calculating it.
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*/
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static void pre_mp_init(void)
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{
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const msr_t syscfg = rdmsr(SYSCFG_MSR);
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if (syscfg.lo & SYSCFG_MSR_TOM2WB)
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x86_setup_mtrrs_with_detect_no_above_4gb();
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else
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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}
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = get_smm_info,
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.relocation_handler = smm_relocation_handler,
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.post_mp_init = global_smi_enable,
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};
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void mp_init_cpus(struct bus *cpu_bus)
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{
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if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
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die_with_post_code(POST_HW_INIT_FAILURE,
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"mp_init_with_smm failed. Halting.\n");
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/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
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mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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/* SMMINFO only needs to be set up when booting from S5 */
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if (!acpi_is_wakeup_s3())
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apm_control(APM_CNT_SMMINFO);
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}
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static void model_17_init(struct device *dev)
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{
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check_mca();
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set_cstate_io_addr();
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amd_update_microcode_from_cbfs();
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_17_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, RAVEN1_B0_CPUID},
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{ X86_VENDOR_AMD, PICASSO_B0_CPUID },
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{ X86_VENDOR_AMD, PICASSO_B1_CPUID },
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{ X86_VENDOR_AMD, RAVEN2_A0_CPUID },
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{ X86_VENDOR_AMD, RAVEN2_A1_CPUID },
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{ 0, 0 },
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};
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static const struct cpu_driver model_17 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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