a244d5edd4
Location in hudson_lpc_port80() was called conditionally. Also move hudson_lpc_decode() call after enable_acpimmio_decode_pmXX() due the change from IO to MMIO using pm_read/write. Change-Id: I38e94e4b04f0a493052cfd3ffdd0a9c2ac0d07fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
113 lines
3.1 KiB
C
113 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <device/pci_ops.h>
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/*
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* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
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*
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* Hardware should enable LPC ROM by pin straps. This function does not
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* handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
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*
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* The HUDSON power-on default is to map 512K ROM space.
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*
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*/
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static void hudson_enable_rom(void)
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{
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u8 reg8;
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pci_devfn_t dev;
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dev = PCI_DEV(0, 0x14, 3);
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/* Decode variable LPC ROM address ranges 1 and 2. */
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reg8 = pci_io_read_config8(dev, 0x48);
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reg8 |= (1 << 3) | (1 << 4);
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pci_io_write_config8(dev, 0x48, reg8);
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/* LPC ROM address range 1: */
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/* Enable LPC ROM range mirroring start at 0x000e(0000). */
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pci_io_write_config16(dev, 0x68, 0x000e);
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/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
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pci_io_write_config16(dev, 0x6a, 0x000f);
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/* LPC ROM address range 2: */
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/*
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* Enable LPC ROM range start at:
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* 0xfff8(0000): 512KB
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* 0xfff0(0000): 1MB
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* 0xffe0(0000): 2MB
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* 0xffc0(0000): 4MB
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*/
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pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
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/* Enable LPC ROM range end at 0xffff(ffff). */
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pci_io_write_config16(dev, 0x6e, 0xffff);
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}
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static void bootblock_southbridge_init(void)
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{
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hudson_enable_rom();
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}
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#if !CONFIG(ROMCC_BOOTBLOCK)
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#include <bootblock_common.h>
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#include <amdblocks/acpimmio.h>
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#include <southbridge/amd/agesa/hudson/hudson.h>
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void bootblock_soc_early_init(void)
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{
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pci_devfn_t dev;
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u32 data;
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bootblock_southbridge_init();
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enable_acpimmio_decode_pm24();
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hudson_lpc_decode();
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if (CONFIG(POST_DEVICE_PCI_PCIE))
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hudson_pci_port80();
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else if (CONFIG(POST_DEVICE_LPC))
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hudson_lpc_port80();
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dev = PCI_DEV(0, 0x14, 3);
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data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
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/* enable 0x2e/0x4e IO decoding for SuperIO */
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pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
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/*
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* Enable FCH to decode TPM associated Memory and IO regions for vboot
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*
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* Enable decoding of TPM cycles defined in TPM 1.2 spec
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* Enable decoding of legacy TPM addresses: IO addresses 0x7f-
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* 0x7e and 0xef-0xee.
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*/
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data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE);
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data |= TPM_12_EN | TPM_LEGACY_EN;
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pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data);
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/*
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* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". This following register setting has been
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* replicated in every reference design since Parmer, so it is
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* believed to be required even though it is not documented in
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* the SoC BKDGs. Without this setting, there is no serial
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* output.
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*/
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pm_write8(0xd2, 0);
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}
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#endif
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