a257efcfcc
Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
143 lines
4.6 KiB
C
143 lines
4.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "AGESA.h"
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#include "amdlib.h"
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#include <spd_bin.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include "FchPlatform.h"
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#include "cbfs.h"
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#include "gpio_ftns.h"
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#include "imc.h"
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#include "hudson.h"
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#include <stdlib.h>
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
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static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_READ_SPD, board_ReadSpd_from_cbfs },
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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//{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_NoopUnsupported }
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/*
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* Hardware Monitor Fan Control
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* Hardware limitation:
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* HWM will fail to read the input temperature via I2C if other
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* software switches the I2C address. AMD recommends using IMC
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* to control fans, instead of HWM.
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*/
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static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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{
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FchParams->Imc.ImcEnable = FALSE;
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FchParams->Hwm.HwMonitorEnable = FALSE;
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FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */
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}
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/**
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* Fch Oem setting callback
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*
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* Configure platform specific Hudson device,
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* such Azalia, SATA, IMC etc.
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*/
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
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{
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AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
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FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
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FchParams->FchReset.SataEnable = hudson_sata_enable();
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FchParams->FchReset.IdeEnable = hudson_ide_enable();
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FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams->FchReset.Xhci1Enable = FALSE;
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} else if (StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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FchParams->Azalia.AzaliaEnable = AzDisable;
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/* Fan Control */
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oem_fan_control(FchParams);
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/* XHCI configuration */
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FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams->Usb.Xhci1Enable = FALSE;
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/* EHCI configuration */
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FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams->Usb.Ehci1Enable = FALSE; // Disable EHCI 0 (port 0 to 3)
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FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
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/* sata configuration */
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FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
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FchParams->Sata.SataDevSlpPort1 = 0;
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FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
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switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
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case SataRaid:
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case SataAhci:
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case SataAhci7804:
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case SataLegacyIde:
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FchParams->Sata.SataIdeMode = FALSE;
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break;
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case SataIde2Ahci:
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case SataIde2Ahci7804:
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default: /* SataNativeIde */
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FchParams->Sata.SataIdeMode = TRUE;
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break;
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}
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}
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printk(BIOS_DEBUG, "Done\n");
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return AGESA_SUCCESS;
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}
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static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status = AGESA_UNSUPPORTED;
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#ifdef __PRE_RAM__
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AGESA_READ_SPD_PARAMS *info = ConfigPtr;
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u8 index = get_spd_offset();
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if (info->MemChannelId > 0)
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return AGESA_UNSUPPORTED;
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if (info->SocketId != 0)
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return AGESA_UNSUPPORTED;
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if (info->DimmId != 0)
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return AGESA_UNSUPPORTED;
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/* Read index 0, first SPD_SIZE bytes of spd.bin file. */
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if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0)
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die("No SPD data\n");
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Status = AGESA_SUCCESS;
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#endif
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return Status;
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}
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