a2701c6005
This reverts commit 78efc4c36c.
The broadcast patch was reverted, so this commit should also
be reverted. The reason for reverting the broadcast patch:
It turned out that sending IPIs via broadcast doesn't work on
Sandybridge. We tried to come up with a solution, but didn't
found any so far. So revert the code for now until we have
a working solution.
Change-Id: I05c27dec55fa681f455215be56dcbc5f22808193
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1380
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
214 lines
3.8 KiB
Plaintext
214 lines
3.8 KiB
Plaintext
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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if BOARD_AMD_TORPEDO
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select DIMM_DDR3
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select DIMM_UNREGISTERED
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select CPU_AMD_AGESA_FAMILY12
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select NORTHBRIDGE_AMD_AGESA_FAMILY12_ROOT_COMPLEX
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select NORTHBRIDGE_AMD_AGESA_FAMILY12
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select SOUTHBRIDGE_AMD_CIMX_SB900
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select SUPERIO_SMSC_KBC1100
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select BOARD_HAS_FADT
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select HAVE_BUS_CONFIG
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_MAINBOARD_RESOURCES
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select HAVE_HARD_RESET
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select LIFT_BSP_APIC_ID
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select SERIAL_CPU_INIT
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select AMDMCT
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_2048
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select ENABLE_APIC_EXT_ID
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select GFXUMA
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config MAINBOARD_DIR
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string
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default amd/torpedo
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config APIC_ID_OFFSET
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hex
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default 0x0
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config MAINBOARD_PART_NUMBER
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string
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default "Torpedo"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x200000
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config MAX_CPUS
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int
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default 4
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config MEM_TRAIN_SEQ
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config IRQ_SLOT_COUNT
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int
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default 11
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config RAMTOP
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hex
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default 0x1000000
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config HEAP_SIZE
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hex
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default 0xc0000
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config STACK_SIZE
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hex
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default 0x10000
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config ACPI_SSDTX_NUM
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int
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default 0
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config RAMBASE
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hex
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default 0x200000
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config SIO_PORT
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hex
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default 0x2e
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config VGA_BIOS
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bool
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default n
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#config VGA_BIOS_FILE
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# string "VGA BIOS path and filename"
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# depends on VGA_BIOS
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# default "rom/video/LlanoGenericVbios.bin"
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config VGA_BIOS_ID
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string "VGA device PCI IDs"
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depends on VGA_BIOS
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default "1002,9641"
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config AHCI_BIOS
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bool
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default n
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#config AHCI_BIOS_FILE
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# string "AHCI ROM path and filename"
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# depends on AHCI_BIOS
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# default "rom/ahci/sb900.bin"
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config AHCI_BIOS_ID
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string "AHCI device PCI IDs"
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depends on AHCI_BIOS
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default "1022,7801"
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config XHC_BIOS
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bool
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default n
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#config XHC_BIOS_FILE
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# string "XHC BIOS path and filename"
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# depends on XHC_BIOS
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# default "rom/xhc/Xhc.rom"
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config XHC_BIOS_ID
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string "XHC device PCI IDs"
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depends on XHC_BIOS
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default "1022,7812"
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config DRIVERS_PS2_KEYBOARD
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bool
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default y
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config WARNINGS_ARE_ERRORS
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bool
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default n
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config CONSOLE_POST
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bool
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depends on !NO_POST
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default y
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config SATA_CONTROLLER_MODE
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hex
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default 0x0
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depends on SOUTHBRIDGE_AMD_CIMX_SB900
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config ONBOARD_LAN
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bool
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default y
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config ONBOARD_1394
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bool
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default y
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config ONBOARD_USB30
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bool
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default n
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config ONBOARD_BLUETOOTH
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bool
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default y
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config ONBOARD_WEBCAM
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bool
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default y
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config ONBOARD_TRAVIS
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bool
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default y
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config ONBOARD_LIGHTSENSOR
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bool
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default n
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endif # BOARD_AMD_TORPEDO
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