a27fba67a0
Since the socket layer is implemented with this CPU model, there could potentially be multiple CPU models included. There can be only one cache_as_ram include, so select it directly within the socket directory. Change-Id: Ia52bb152276eddfd1fb33ddb7f5d153ab8e8163c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15757 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
5 lines
135 B
Makefile
5 lines
135 B
Makefile
ramstage-y += model_106cx_init.c
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subdirs-y += ../../x86/name
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
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