a2bc2540c2
Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
63 lines
1.5 KiB
C
63 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootmode.h>
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#include <boot/coreboot_tables.h>
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#include <device/device.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <ec/quanta/ene_kb3940q/ec.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "ec.h"
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#include "onboard.h"
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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/* lid switch value from EC */
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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/* Power Button - Hardcode Low as power button may still be
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* pressed when read here.*/
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{-1, ACTIVE_HIGH, 0, "power"},
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/* Was VGA Option ROM loaded? */
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/* -1 indicates that this is a pseudo GPIO */
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_write_protect_state(void)
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{
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return !get_gpio(WP_GPIO);
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}
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int get_lid_switch(void)
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{
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return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1;
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}
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/* FIXME: VBOOT reads this in ENV_SEPARATE_ROMSTAGE. */
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int get_recovery_mode_switch(void)
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{
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if (ENV_RAMSTAGE)
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return (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO);
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return 0;
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME),
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};
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DECLARE_CROS_GPIOS(cros_gpios);
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int get_ec_is_trusted(void)
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{
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/* Do not have a Chrome EC involved in entering recovery mode;
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Always return trusted. */
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return 1;
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}
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