a2c83fb9f9
This patch updates PMC API name from `pmc_send_pci_enum_done` to `pmc_send_bios_reset_pci_enum_done` to inform PMC IPC about BIOS done is also set along with PMC enumeration being done. BUG=b:270942083 TEST=Able to build and boot google/rex. Change-Id: I1cf8cb1ecadeb68c109be6b0e751a3f2c448ae4f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
61 lines
1.6 KiB
C
61 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Alder Lake Processor PCH Datasheet
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* Document number: 621483
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* Chapter number: 4
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*/
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#include <device/mmio.h>
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#include <intelblocks/cfg.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pmclib.h>
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#include <intelpch/lockdown.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <stdint.h>
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/* PCR PSTH Control Register */
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#define PCR_PSTH_CTRLREG 0x1d00
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#define PSTH_CTRLREG_IOSFPTCGE (1 << 2)
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static void pmc_lockdown_cfg(int chipset_lockdown)
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{
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uint8_t *pmcbase = pmc_mmio_regs();
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/* PMSYNC */
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setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
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/* Lock down ABASE and sleep stretching policy */
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setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
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if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
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setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
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if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
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setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK);
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setbits32(pmcbase + SSML, SSML_SSL_EN);
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setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK |
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PM_CFG_XRAM_READ_DISABLE);
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}
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/* Send PMC IPC to inform about both BIOS Reset and PCI enumeration done */
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pmc_send_bios_reset_pci_enum_done();
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}
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static void pch_lockdown_cfg(void)
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{
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if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
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return;
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/* Enable IOSF Primary Trunk Clock Gating */
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pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
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}
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void soc_lockdown_config(int chipset_lockdown)
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{
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/* PMC lock down configuration */
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pmc_lockdown_cfg(chipset_lockdown);
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/* PCH lock down configuration */
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pch_lockdown_cfg();
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}
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