4513020064
The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include "i82801gx.h"
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int southbridge_detect_s3_resume(void)
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{
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u32 reg32;
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/* Read PM1_CNT */
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reg32 = inl(DEFAULT_PMBASE + 0x04);
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printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
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if (((reg32 >> 10) & 7) == 5) {
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if (!acpi_s3_resume_allowed()) {
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printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
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} else {
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printk(BIOS_DEBUG, "Resume from S3 detected.\n");
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/* Clear SLP_TYPE. This will break stage2 but
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* we care for that when we get there.
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*/
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outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
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return 1;
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}
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}
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return 0;
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}
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