a3f060748b
1. Supermicro H8QGI mainboard update to support both family10 Revison D processor and family15 model 00-0fh processor in one binary image. 2. RD890/SR56X0 IO hub CIMX wrapper support. 3. SP5100/SB700 southbridge CIMX wrapper support. Both 8 cores and 16 Cores InterLagos Opteron Processor are tested on this platform. Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested. Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/567 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
67 lines
1.9 KiB
C
67 lines
1.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <reset.h>
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#include <arch/io.h> /*inb, outb*/
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#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/
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#define HT_INIT_CONTROL 0x6C
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#define HTIC_BIOSR_Detect (1<<5)
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#if CONFIG_MAX_PHYSICAL_CPUS > 32
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#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
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#else
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#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
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#endif
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static inline void set_bios_reset(void)
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{
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u32 nodes;
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u32 htic;
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device_t dev;
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int i;
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nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
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for(i = 0; i < nodes; i++) {
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dev = NODE_PCI(i, 0);
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htic = pci_read_config32(dev, HT_INIT_CONTROL);
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htic &= ~HTIC_BIOSR_Detect;
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pci_write_config32(dev, HT_INIT_CONTROL, htic);
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}
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}
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void hard_reset(void)
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{
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set_bios_reset();
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/* Try rebooting through port 0xcf9 */
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/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
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outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
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outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
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}
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//SbReset();
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void soft_reset(void)
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{
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set_bios_reset();
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/* link reset */
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outb(0x06, 0x0cf9);
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}
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