a43048d371
cpu of a certain type and to eliminate the cpu p5 cpu p6 cpu k7 nonsense in the old config files. Next step is to hook into Eric's pci device stuff. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
81 lines
1.6 KiB
C
81 lines
1.6 KiB
C
/* Needed so the AMD K8 runs correctly. */
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#include <console/console.h>
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#include <mem.h>
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#include <cpu/p6/msr.h>
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#include <cpu/k8/mtrr.h>
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#include <device/device.h>
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#include <device/chip.h>
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#include "chip.h"
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void k8_cpufixup(struct mem_range *mem)
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{
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unsigned long mmio_basek, tomk;
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unsigned long i;
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msr_t msr;
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/* Except for the PCI MMIO hold just before 4GB there are no
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* significant holes in the address space, so just account
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* for those two and move on.
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*/
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mmio_basek = tomk = 0;
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for(i = 0; mem[i].sizek; i++) {
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unsigned long topk;
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topk = mem[i].basek + mem[i].sizek;
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if (tomk < topk) {
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tomk = topk;
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}
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if ((topk < 4*1024*1024) && (mmio_basek < topk)) {
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mmio_basek = topk;
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}
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}
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if (mmio_basek > tomk) {
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mmio_basek = tomk;
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}
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/* Setup TOP_MEM */
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msr.hi = mmio_basek >> 22;
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msr.lo = mmio_basek << 10;
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wrmsr(TOP_MEM, msr);
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/* Setup TOP_MEM2 */
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msr.hi = tomk >> 22;
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msr.lo = tomk << 10;
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wrmsr(TOP_MEM2, msr);
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/* zero the IORR's before we enable to prevent
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* undefined side effects.
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*/
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msr.lo = msr.hi = 0;
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for(i = IORR_FIRST; i <= IORR_LAST; i++) {
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wrmsr(i, msr);
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}
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msr = rdmsr(SYSCFG_MSR);
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msr.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_TOM2En;
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wrmsr(SYSCFG_MSR, msr);
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}
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static
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void k8_enable(struct chip *chip, enum chip_pass pass)
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{
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struct cpu_k8_config *conf = (struct cpu_k8_config *)chip->chip_info;
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switch (pass) {
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case CONF_PASS_PRE_CONSOLE:
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break;
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default:
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/* nothing yet */
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break;
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}
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}
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struct chip_control cpu_k8_control = {
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enable: k8_enable,
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name: "AMD K8"
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};
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