a513519df0
Instead of pushing the same code into each mainboard for configuring the the UART pads and initializing the host contoller provide a function to perform all the actions on behalf of the mainboard. The set of pads configured is dictated by the CONFIG_UART_FOR_CONSOLE Kconfig option. Change-Id: I06c499c7ee056b970468e0386d4bb1bc26537247 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13792 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
92 lines
2.6 KiB
C
92 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <console/uart.h>
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#include <device/pci.h>
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#include <soc/gpio.h>
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#include <soc/uart.h>
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#include <soc/pci_devs.h>
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static void lpss_uart_write(uint16_t reg, uint32_t val)
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{
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uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg;
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write32((void *)base, val);
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}
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static inline int invalid_uart_for_console(void)
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{
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/* There are actually only 2 UARTS, and they are named UART1 and
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* UART2. They live at pci functions 1 and 2 respectively. */
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if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1)
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return 1;
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return 0;
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}
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void lpss_console_uart_init(void)
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{
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uint32_t clk_sel;
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device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
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if (invalid_uart_for_console())
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return;
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/* Enable BAR0 for the UART -- this is where the 8250 registers hide */
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pci_write_config32(uart, PCI_BASE_ADDRESS_0,
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CONFIG_CONSOLE_UART_BASE_ADDRESS);
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/* Enable memory access and bus master */
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pci_write_config32(uart, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* Take UART out of reset */
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lpss_uart_write(UART_RESET, UART_RESET_UART_EN);
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/* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */
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clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a);
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/* Set M and N divisor inputs and enable clock */
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lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE);
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lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN);
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}
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uintptr_t uart_platform_base(int idx)
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{
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return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
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}
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unsigned int uart_platform_refclk(void)
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{
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/* That's within 0.5% of the actual value we've set earlier */
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return 115200 * 16;
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}
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static const struct pad_config uart_gpios[] = {
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PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
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PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */
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PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */
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PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */
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};
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void soc_console_uart_init(void)
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{
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/* Get a 0-based pad index. See invalid_uart_for_console() above. */
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const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;
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if (invalid_uart_for_console())
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return;
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/* Configure the 2 pads per UART. */
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gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
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lpss_console_uart_init();
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}
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