a56ff9087b
Since the HD audio controller in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and audio still works Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79118 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/mmio.h>
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#include <delay.h>
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#include <device/azalia_device.h>
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#include "chip.h"
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#include "pch.h"
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static int codec_detect(u8 *base)
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{
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u8 reg8;
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if (azalia_exit_reset(base) < 0)
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goto no_codec;
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/* Write back the value once reset bit is set. */
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write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
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/* Read in Codec location (BAR + 0xe)[2..0] */
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reg8 = read8(base + HDA_STATESTS_REG);
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reg8 &= 0x0f;
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if (!reg8)
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goto no_codec;
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return reg8;
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no_codec:
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/* Codec not found, put HDA back in reset */
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azalia_enter_reset(base);
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printk(BIOS_DEBUG, "Azalia: No codec!\n");
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return 0;
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}
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static void azalia_init(struct device *dev)
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{
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u8 *base;
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struct resource *res;
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u32 codec_mask;
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u32 reg32;
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res = probe_resource(dev, PCI_BASE_ADDRESS_0);
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if (!res)
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return;
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// NOTE this will break as soon as the Azalia gets a bar above 4G.
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// Is there anything we can do about it?
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base = res2mmio(res, 0, 0);
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printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
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if (RCBA32(CIR31) & (1 << 31)) {
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reg32 = pci_read_config32(dev, 0x120);
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reg32 &= 0xf8ffff01;
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reg32 |= (1 << 24); // 2 << 24 for server
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reg32 |= RCBA32(CIR31) & 0xfe;
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pci_write_config32(dev, 0x120, reg32);
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pci_or_config16(dev, 0x78, 1 << 11);
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} else
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printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
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pci_and_config32(dev, 0x114, ~0xfe);
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// Set VCi enable bit
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pci_or_config32(dev, 0x120, 1 << 31);
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// Enable HDMI codec:
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pci_or_config32(dev, 0xc4, 1 << 1);
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pci_or_config8(dev, 0x43, 1 << 6);
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/* Additional programming steps */
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pci_or_config32(dev, 0xc4, 1 << 13);
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pci_or_config32(dev, 0xc4, 1 << 10);
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pci_and_config32(dev, 0xd0, ~(1 << 31));
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if (dev->device == 0x1e20) {
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/* Additional step on Panther Point */
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pci_or_config32(dev, 0xc4, 1 << 17);
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}
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/* Set Bus Master */
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
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pci_write_config8(dev, 0x3c, 0x0a); // unused?
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/* Codec Initialization Programming Sequence */
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/* Take controller out of reset */
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reg32 = read32(base + HDA_GCTL_REG);
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reg32 |= HDA_GCTL_CRST;
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write32(base + HDA_GCTL_REG, reg32);
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/* Wait 1ms */
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udelay(1000);
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// Select Azalia mode. This needs to be controlled via devicetree.cb
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pci_or_config8(dev, 0x40, 1); // Audio Control
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// Docking not supported
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pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
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codec_mask = codec_detect(base);
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if (codec_mask) {
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printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
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azalia_codecs_init(base, codec_mask);
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}
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/* Enable dynamic clock gating */
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pci_update_config8(dev, 0x43, ~0x07, (1 << 2) | (1 << 0));
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}
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static const char *azalia_acpi_name(const struct device *dev)
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{
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return "HDEF";
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}
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struct device_operations bd82x6x_azalia_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = azalia_init,
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.ops_pci = &pci_dev_ops_pci,
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.acpi_name = azalia_acpi_name,
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};
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