a63719407f
This was added to handle cases of Intel FSP platforms that had EARLY_CBMEM_INIT but could not migrate CAR variables to CBMEM. These boards were recently fixed. To support combination of EARLY_CBMEM_INIT without CAR migration was added maintenance effort with little benefits. You had no CBMEM console for romstage and the few timestamps you could store were circulated via PCI scratchpads or CMOS nvram. Change-Id: I5cffb7f2b14c45b67ee70cf48be4d7a4c9e5f761 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8636 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
89 lines
2.4 KiB
Plaintext
89 lines
2.4 KiB
Plaintext
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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config CPU_AMD_AGESA
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bool
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default y if CPU_AMD_AGESA_FAMILY10
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default y if CPU_AMD_AGESA_FAMILY12
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default y if CPU_AMD_AGESA_FAMILY14
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default y if CPU_AMD_AGESA_FAMILY15
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default y if CPU_AMD_AGESA_FAMILY15_TN
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default y if CPU_AMD_AGESA_FAMILY15_RL
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default y if CPU_AMD_AGESA_FAMILY16_KB
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default n
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select TSC_SYNC_LFENCE
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select UDELAY_LAPIC
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select LAPIC_MONOTONIC_TIMER
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select SPI_FLASH if HAVE_ACPI_RESUME
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if CPU_AMD_AGESA
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config UDELAY_IO
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bool
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default n
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config XIP_ROM_SIZE
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hex
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default 0x100000
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help
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Overwride the default write through caching size as 1M Bytes.
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On some AMD platforms, one socket supports 2 or more kinds of
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processor family, compiling several CPU families agesa code
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will increase the romstage size.
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In order to execute romstage in place on the flash ROM,
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more space is required to be set as write through caching.
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config UDELAY_LAPIC_FIXED_FSB
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int
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default 200
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# TODO: Sync these with definitions in AGESA vendorcode.
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# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
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# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
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config DCACHE_RAM_BASE
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hex
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default 0x30000
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config DCACHE_RAM_SIZE
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hex
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default 0x10000
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config S3_DATA_POS
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hex
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default 0xFFFF0000
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config S3_DATA_SIZE
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int
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default 32768
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endif # CPU_AMD_AGESA
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source src/cpu/amd/agesa/family10/Kconfig
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source src/cpu/amd/agesa/family12/Kconfig
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source src/cpu/amd/agesa/family14/Kconfig
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source src/cpu/amd/agesa/family15/Kconfig
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source src/cpu/amd/agesa/family15tn/Kconfig
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source src/cpu/amd/agesa/family15rl/Kconfig
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source src/cpu/amd/agesa/family16kb/Kconfig
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