AMD GX and LX processors. This aguments the previous code, which was very specific to the OLPC platform with general purpose support and better integration with the VSA and CPUs. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
299 lines
6.8 KiB
C
299 lines
6.8 KiB
C
//#include <device/smbus_def.h>
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#define SMBUS_ERROR -1
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#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
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#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
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#define SMB_SDA 0x00
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#define SMB_STS 0x01
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#define SMB_CTRL_STS 0x02
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#define SMB_CTRL1 0x03
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#define SMB_ADD 0x04
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#define SMB_CTRL2 0x05
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#define SMB_CTRL3 0x06
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#define SMB_STS_SLVSTP (0x01 << 7)
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#define SMB_STS_SDAST (0x01 << 6)
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#define SMB_STS_BER (0x01 << 5)
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#define SMB_STS_NEGACK (0x01 << 4)
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#define SMB_STS_STASTR (0x01 << 3)
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#define SMB_STS_NMATCH (0x01 << 2)
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#define SMB_STS_MASTER (0x01 << 1)
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#define SMB_STS_XMIT (0x01 << 0)
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#define SMB_CSTS_TGSCL (0x01 << 5)
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#define SMB_CSTS_TSDA (0x01 << 4)
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#define SMB_CSTS_GCMTCH (0x01 << 3)
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#define SMB_CSTS_MATCH (0x01 << 2)
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#define SMB_CSTS_BB (0x01 << 1)
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#define SMB_CSTS_BUSY (0x01 << 0)
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#define SMB_CTRL1_STASTRE (0x01 << 7)
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#define SMB_CTRL1_NMINTE (0x01 << 6)
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#define SMB_CTRL1_GCMEN (0x01 << 5)
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#define SMB_CTRL1_ACK (0x01 << 4)
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#define SMB_CTRL1_RSVD (0x01 << 3)
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#define SMB_CTRL1_INTEN (0x01 << 2)
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#define SMB_CTRL1_STOP (0x01 << 1)
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#define SMB_CTRL1_START (0x01 << 0)
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#define SMB_ADD_SAEN (0x01 << 7)
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#define SMB_CTRL2_ENABLE 0x01
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#define SMBUS_TIMEOUT (100*1000*10)
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#define SMBUS_STATUS_MASK 0xfbff
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static void smbus_delay(void)
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{
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inb(0x80);
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}
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static int smbus_wait(unsigned smbus_io_base) {
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unsigned long loops = SMBUS_TIMEOUT;
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unsigned char val;
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do {
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smbus_delay();
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val = inb(smbus_io_base + SMB_STS);
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if ((val & SMB_STS_SDAST) != 0)
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break;
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if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
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printk_debug("SMBUS WAIT ERROR %x\n", val);
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return SMBUS_ERROR;
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}
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} while(--loops);
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outb(0, smbus_io_base + SMB_STS);
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return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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static int smbus_write(unsigned smbus_io_base, unsigned char byte) {
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outb(byte, smbus_io_base + SMB_SDA);
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return smbus_wait(smbus_io_base);
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}
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/* generate a smbus start condition */
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static int smbus_start_condition(unsigned smbus_io_base)
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{
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unsigned char val;
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/* issue a START condition */
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val = inb(smbus_io_base + SMB_CTRL1);
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outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
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/* check for bus conflict */
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val = inb(smbus_io_base + SMB_STS);
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if ((val & SMB_STS_BER) != 0)
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return SMBUS_ERROR;
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return smbus_wait(smbus_io_base);
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}
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static int smbus_check_stop_condition(unsigned smbus_io_base)
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{
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unsigned char val;
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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/* check for SDA status */
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do {
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smbus_delay();
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val = inb(smbus_io_base + SMB_CTRL1);
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if ((val & SMB_CTRL1_STOP) == 0) {
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break;
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}
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} while(--loops);
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return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Make sure everything is cleared and ready to go */
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val = inb(smbus_io_base + SMB_CTRL1);
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outb(val & ~(SMB_CTRL1_STASTRE | SMB_CTRL1_NMINTE),
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smbus_io_base + SMB_CTRL1);
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outb(SMB_STS_BER | SMB_STS_NEGACK | SMB_STS_STASTR,
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smbus_io_base + SMB_STS);
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val = inb(smbus_io_base + SMB_CTRL_STS);
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outb(val | SMB_CSTS_BB, smbus_io_base + SMB_CTRL_STS);
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}
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static int smbus_stop_condition(unsigned smbus_io_base)
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{
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unsigned char val;
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val = inb(smbus_io_base + SMB_CTRL1);
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outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
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return 0;
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}
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static int smbus_ack(unsigned smbus_io_base, int state)
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{
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unsigned char val = inb(smbus_io_base + SMB_CTRL1);
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if (state)
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outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
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else
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outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
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return 0;
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}
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static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
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{
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unsigned char val;
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/* send the slave address */
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outb(device, smbus_io_base + SMB_SDA);
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/* check for bus conflict and NACK */
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val = inb(smbus_io_base + SMB_STS);
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if (((val & SMB_STS_BER) != 0) ||
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((val & SMB_STS_NEGACK) != 0)) {
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printk_debug("SEND SLAVE ERROR (%x)\n", val);
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return SMBUS_ERROR;
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}
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return smbus_wait(smbus_io_base);
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}
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static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
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{
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unsigned char val;
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/* send the command */
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outb(command, smbus_io_base + SMB_SDA);
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/* check for bus conflict and NACK */
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val = inb(smbus_io_base + SMB_STS);
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if (((val & SMB_STS_BER) != 0) ||
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((val & SMB_STS_NEGACK) != 0))
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return SMBUS_ERROR;
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return smbus_wait(smbus_io_base);
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}
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static void _doread(unsigned smbus_io_base, unsigned char device,
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unsigned char address, unsigned char *data, int count)
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{
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int ret;
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int index = 0;
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unsigned char val;
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if ((ret = smbus_check_stop_condition(smbus_io_base)))
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goto err;
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index++;
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if ((ret = smbus_start_condition(smbus_io_base)))
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goto err;
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index++; /* 2 */
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if ((ret = smbus_send_slave_address(smbus_io_base, device)))
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goto err;
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index++;
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if ((ret = smbus_send_command(smbus_io_base, address)))
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goto err;
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index++;
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if ((ret = smbus_start_condition(smbus_io_base)))
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goto err;
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/* Clear the ack for multiple byte reads */
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smbus_ack(smbus_io_base, (count == 1) ? 1 : 0);
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index++;
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if ((ret = smbus_send_slave_address(smbus_io_base, device | 0x01)))
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goto err;
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while(count) {
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/* Set the ACK if this is the next to last byte */
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smbus_ack(smbus_io_base, (count == 2) ? 1 : 0);
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/* Set the stop bit if this is the last byte to read */
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if (count == 1)
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smbus_stop_condition(smbus_io_base);
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val = inb(smbus_io_base + SMB_SDA);
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*data++ = val;
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if (count > 1) {
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int ret = smbus_wait(smbus_io_base);
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if (ret)
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return ret;
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}
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count--;
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}
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return;
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err:
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printk_debug("SMBUS READ ERROR (%d): %d\n", index, ret);
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}
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static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
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unsigned char device,
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unsigned char address)
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{
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unsigned char val = 0;
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_doread(smbus_io_base, device, address, &val, sizeof(val));
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return val;
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}
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static unsigned short do_smbus_read_word(unsigned smbus_io_base,
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unsigned char device, unsigned char address)
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{
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unsigned short val = 0;
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_doread(smbus_io_base, device, address, (unsigned char *) &val,
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sizeof(val));
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return val;
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}
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static int _dowrite(unsigned smbus_io_base, unsigned char device,
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unsigned char address, unsigned char *data, int count) {
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int ret;
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if ((ret = smbus_check_stop_condition(smbus_io_base)))
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goto err;
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if ((ret = smbus_start_condition(smbus_io_base)))
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goto err;
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if ((ret = smbus_send_slave_address(smbus_io_base, device)))
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goto err;
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if ((ret = smbus_send_command(smbus_io_base, address)))
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goto err;
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while(count) {
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if ((ret = smbus_write(smbus_io_base, *data++)))
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goto err;
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count--;
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}
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smbus_stop_condition(smbus_io_base);
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return 0;
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err:
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printk_debug("SMBUS WRITE ERROR: %d\n", ret);
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return -1;
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}
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static int do_smbus_write_byte(unsigned smbus_io_base, unsigned char device,
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unsigned char address, unsigned char data)
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{
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return _dowrite(smbus_io_base, device, address,
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(unsigned char *) &data, 1);
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}
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static int do_smbus_write_word(unsigned smbus_io_base, unsigned char device, unsigned char address,
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unsigned short data)
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{
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return _dowrite(smbus_io_base, device ,address, (unsigned char *) &data, 2);
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}
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