Elyes HAOUAS a6a396ddb6 cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35 ...

Regarding 64 and IA-32 Architectures Software Developer’s Manual, the register
name of the msr at 0x35 is MSR_CORE_THREAD_COUNT.

Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33015
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2019-06-21 08:55:44 +00:00

..

acpi.c

cpu/intel/model_206{5,a}x: Rework acpi/cpu.asl

2018-11-30 21:52:10 +00:00

bootblock.c

coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

2019-03-08 08:33:24 +00:00

chip.h

tree: drop last paragraph of GPL copyright header

2015-10-31 21:37:39 +01:00

common.c

src: Move common IA-32 MSRs to <cpu/x86/msr.h>

2018-10-11 21:06:53 +00:00

finalize.c

src: Remove unneeded include "{arch,cpu}/cpu.h"

2018-11-12 09:22:18 +00:00

Kconfig

nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGE

2019-05-12 15:03:03 +00:00

Makefile.inc

security/vboot: Add measured boot mode

2019-02-25 22:29:16 +00:00

model_206ax_init.c

cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35

2019-06-21 08:55:44 +00:00

model_206ax.h

cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35

2019-06-21 08:55:44 +00:00

stage_cache.c

cpu/intel/sandybridge: Put stage cache into TSEG

2018-04-10 09:30:21 +00:00

tsc_freq.c

cpu/intel/model_206ax: Use tsc monotonic timer

2017-06-09 16:27:19 +02:00