a6b0922aa1
Change-Id: I5c75409fd3b7b018e402c471cbd856eca20278b7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49757 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
33 lines
1.1 KiB
C
33 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/bootblock.h>
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#include <assert.h>
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#include <device/pci_ops.h>
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#include <types.h>
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#include "i945.h"
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static uint32_t encode_pciexbar_length(void)
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{
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switch (CONFIG_MMCONF_BUS_NUMBER) {
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case 256: return 0 << 1;
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case 128: return 1 << 1;
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case 64: return 2 << 1;
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default: return dead_code_t(uint32_t);
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}
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}
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void bootblock_early_northbridge_init(void)
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{
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/*
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* The "io" variant of the config access is explicitly used to setup the PCIEXBAR
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* because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit
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* config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final assumption is that
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* no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
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*/
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const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
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pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
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}
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