a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
104 lines
2.9 KiB
ArmAsm
104 lines
2.9 KiB
ArmAsm
/*
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* Early initialization code for ARMv7 architecture.
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*
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* This file is based off of the OMAP3530/ARM Cortex start.S file from Das
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* U-Boot, which itself got the file from armboot.
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*
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* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
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* Copyright (c) 2013 The Chromium OS Authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/asm.h>
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.arm
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/*
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* Just in case the maskrom or the vendor basic firmware passes on a
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* parameter when calling the bootblock, store it here for handling by C
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* code.
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*/
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.section .bss, "aw" @nobits
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.global maskrom_param
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maskrom_param:
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.word 0
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ENTRY(_start)
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/*
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* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
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* aborts may happen early and crash before the abort handlers are
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* installed, but at least the problem will show up near the code that
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* causes it.
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*/
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msr cpsr_cxf, #0xdf
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bl _thumb_start
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ENDPROC(_start)
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.thumb
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ENTRY(_thumb_start)
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/* Preserve the maskrom passed value, if any */
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mov r10, r0
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bl arm_init_caches
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/*
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* From Cortex-A Series Programmer's Guide:
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* Only CPU 0 performs initialization. Other CPUs go into WFI
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* to do this, first work out which CPU this is
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* this code typically is run before any other initialization step
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*/
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mrc p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register
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and r1, r1, #0x3 @ Extract CPU ID bits
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cmp r1, #0
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bne wait_for_interrupt @ If this is not core0, wait
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/*
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* Initialize the stack to a known value. This is used to check for
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* stack overflow later in the boot process.
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*/
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ldr r0, =_stack
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ldr r1, =_estack
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ldr r2, =0xdeadbeef
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init_stack_loop:
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str r2, [r0]
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add r0, #4
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cmp r0, r1
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bne init_stack_loop
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call_bootblock:
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/* Restore parameter passed in by maskrom/vendor firmware. */
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ldr r0, =maskrom_param
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str r10, [r0]
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/* Set stackpointer in internal RAM to call bootblock main() */
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ldr sp, =_estack
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ldr r0,=0x00000000
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/*
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* The current design of cpu_info places the struct at the top of the
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* stack. Free enough space to accomodate for that, but make sure it's
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* 8-byte aligned for ABI compliance.
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*/
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sub sp, sp, #16
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bl main
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wait_for_interrupt:
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wfi
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mov pc, lr @ back to my caller
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ENDPROC(_thumb_start)
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