9dccf1c40b
Some SOCs (like pistachio, for instance) provide an 8250 compatible
UART, which has the same register layout, but mapped to a bus of a
different width.
Instead of adding a new driver for these controllers, it is better to
have coreboot report UART register width to libpayload, and have it
adjust the offsets accordingly when accessing the UART.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the rest of the patches integrated depthcharge console messages
show up when running on the FPGA board
Change-Id: I30b742146069450941164afb04641b967a214d6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42
Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240027
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9738
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
56 lines
1.3 KiB
C
56 lines
1.3 KiB
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright (C) 2013 Google, Inc.
|
|
*
|
|
* This software is licensed under the terms of the GNU General Public
|
|
* License version 2, as published by the Free Software Foundation, and
|
|
* may be copied, distributed, and modified under those terms.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#include <boot/coreboot_tables.h>
|
|
#include <console/uart.h>
|
|
|
|
static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data)
|
|
{
|
|
*uart_base = (unsigned int)data;
|
|
}
|
|
|
|
void uart_init(int idx)
|
|
{
|
|
}
|
|
|
|
void uart_tx_byte(int idx, unsigned char data)
|
|
{
|
|
unsigned int *uart_base = uart_platform_baseptr(idx);
|
|
pl011_uart_tx_byte(uart_base, data);
|
|
}
|
|
|
|
void uart_tx_flush(int idx)
|
|
{
|
|
}
|
|
|
|
unsigned char uart_rx_byte(int idx)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#ifndef __PRE_RAM__
|
|
void uart_fill_lb(void *data)
|
|
{
|
|
struct lb_serial serial;
|
|
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
|
|
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
|
|
serial.baud = default_baudrate();
|
|
serial.regwidth = 1;
|
|
lb_add_serial(&serial, data);
|
|
|
|
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
|
|
}
|
|
#endif
|