419bfbc1f1
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
112 lines
3.7 KiB
C
112 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef CPU_INTEL_SPEEDSTEP_H
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#define CPU_INTEL_SPEEDSTEP_H
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#include <stdint.h>
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/* Magic value used to locate speedstep configuration in the device tree */
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#define SPEEDSTEP_APIC_MAGIC 0xACAC
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/* MWAIT coordination I/O base address. This must match
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* the \_PR_.CP00 PM base address.
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*/
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#define PMB0_BASE 0x510
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/* PMB1: I/O port that triggers SMI once cores are in the same state.
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* See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
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*/
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#define PMB1_BASE 0x800
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/* Speedstep related MSRs */
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#define MSR_THERM2_CTL 0x19D
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#define MSR_EBC_FREQUENCY_ID 0x2c
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#define MSR_FSB_FREQ 0xcd
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#define MSR_FSB_CLOCK_VCC 0xce
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#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
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#define MSR_PMG_IO_BASE_ADDR 0xe3
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#define MSR_PMG_IO_CAPTURE_ADDR 0xe4
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#define MSR_EXTENDED_CONFIG 0xee
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#define FREQ_LIMIT_RATIO 0x1AD
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typedef struct {
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uint8_t dynfsb : 1; /* whether this is SLFM */
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uint8_t nonint : 1; /* add .5 to ratio */
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uint8_t ratio : 6;
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uint8_t vid;
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uint8_t is_turbo;
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uint8_t is_slfm;
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uint32_t power;
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} sst_state_t;
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#define SPEEDSTEP_RATIO_SHIFT 8
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#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT)
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#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT)
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#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT)
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#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT)
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#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT)
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#define SPEEDSTEP_VID_MASK 0x3f
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#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((sst_state_t){ \
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0, /* dynfsb won't be read. */ \
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((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \
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(((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \
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>> SPEEDSTEP_RATIO_SHIFT), \
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(val & mask) & SPEEDSTEP_VID_MASK, \
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0, /* not turbo by default */ \
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0, /* not slfm by default */ \
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0 /* power is hardcoded in software. */ \
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})
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#define SPEEDSTEP_ENCODE_STATE(state) ( \
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((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \
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((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \
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((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \
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((uint16_t)(state).vid & SPEEDSTEP_VID_MASK))
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#define SPEEDSTEP_DOUBLE_RATIO(state) ( \
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((uint8_t)(state).ratio * 2) + (state).nonint)
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typedef struct {
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sst_state_t slfm;
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sst_state_t min;
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sst_state_t max;
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sst_state_t turbo;
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} sst_params_t;
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/* Looking at core2's spec, the highest normal bus ratio for an eist enabled
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processor is 14, the lowest is always 6. This makes 5 states with the
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minimal step width of 2. With turbo mode and super LFM we have at most 7. */
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#define SPEEDSTEP_MAX_NORMAL_STATES 5
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#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2)
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typedef struct {
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/* Table of p-states for EMTTM and ACPI by decreasing performance. */
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sst_state_t states[SPEEDSTEP_MAX_STATES];
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int num_states;
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} sst_table_t;
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void speedstep_gen_pstates(sst_table_t *);
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#define SPEEDSTEP_MAX_POWER_YONAH 31000
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#define SPEEDSTEP_MIN_POWER_YONAH 13100
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#define SPEEDSTEP_MAX_POWER_MEROM 35000
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#define SPEEDSTEP_MIN_POWER_MEROM 25000
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#define SPEEDSTEP_SLFM_POWER_MEROM 12000
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#define SPEEDSTEP_MAX_POWER_PENRYN 35000
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#define SPEEDSTEP_MIN_POWER_PENRYN 15000
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#define SPEEDSTEP_SLFM_POWER_PENRYN 12000
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#endif /* CPU_INTEL_SPEEDSTEP_H */
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