a84a99b994
- Replace $(PWD) with $(CURDIR) in Makefiles. I don't know why the Solaris version behaves differently, but CURDIR is a safe choice on gnu make (and we require gnu make already) - Use tail -1 instead of tail -n1 in a file that already relies on tail -1 support in another place - Use tail -1 as alternative to tail -n1 in another place - Use #define for ulong_t in romcc, as that name is used on Solaris - Avoid fprinting a null pointer. The standard doesn't mandate that this is a special case, and Solaris doesn't implement it that way. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
271 lines
7.7 KiB
Plaintext
271 lines
7.7 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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##
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## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
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##
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##
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## Only use the option table in a normal image
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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include /config/nofailovercalculation.lb
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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driver rtl8168.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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if HAVE_SMI_HANDLER smmobject mainboard_smi.o end
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if HAVE_ACPI_TABLES
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object fadt.o
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object acpi_tables.o
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makerule dsdt.c
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depends "$(MAINBOARD)/dsdt.asl"
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action "iasl -p dsdt -tc $(MAINBOARD)/dsdt.asl"
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action "mv $(CURDIR)/dsdt.hex dsdt.c"
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end
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object ./dsdt.o
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end
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object reset.o
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if CONFIG_USE_INIT
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makerule ./auto.o
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depends "$(MAINBOARD)/auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/auto.c -o $@"
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end
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else
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/auto.c -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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ldscript /cpu/x86/car/cache_as_ram.lds
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end
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## Setup Cache-As-Ram
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##
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mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
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###
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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if CONFIG_USE_INIT
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initobject auto.o
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else
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mainboardinit ./auto.inc
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end
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/intel/i945
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device apic_cluster 0 on
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chip cpu/intel/socket_mFCPGA478
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 00.0 on end # host bridge
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device pci 01.0 off end # i945 PCIe root port
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chip drivers/pci/onboard
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device pci 02.0 on end # vga controller
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# register "rom_address" = "0xfffc0000" # 256 KB image
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# register "rom_address" = "0xfff80000" # 512 KB image
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register "rom_address" = "0xfff00000" # 1 MB image
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end
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device pci 02.1 on end # display controller
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chip southbridge/intel/i82801gx
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register "pirqa_routing" = "0x05"
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register "pirqb_routing" = "0x07"
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register "pirqc_routing" = "0x05"
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register "pirqd_routing" = "0x07"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x06"
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi13_routing" = "1"
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register "ide_legacy_combined" = "0x1"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x0"
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe
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device pci 1c.1 on end # PCIe
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device pci 1c.2 on end # PCIe
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#device pci 1c.3 off end # PCIe port 4
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#device pci 1c.4 off end # PCIe port 5
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#device pci 1c.5 off end # PCIe port 6
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device pci 1d.0 on end # USB UHCI
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device pci 1d.1 on end # USB UHCI
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device pci 1d.2 on end # USB UHCI
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device pci 1d.3 on end # USB UHCI
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device pci 1d.7 on end # USB2 EHCI
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device pci 1e.0 on end # PCI bridge
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#device pci 1e.2 off end # AC'97 Audio
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#device pci 1e.3 off end # AC'97 Modem
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device pci 1f.0 on # LPC bridge
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chip superio/winbond/w83627thg
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device pnp 2e.0 off # Floppy
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end
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device pnp 2e.1 off # Parport
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end
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device pnp 2e.2 on
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on
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io 0x60 = 0x2f8
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irq 0x70 = 3
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irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
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end
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device pnp 2e.5 on # Keyboard+Mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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irq 0xf0 = 0x82 # HW accel A20.
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end
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device pnp 2e.7 on # GPIO1, GAME, MIDI
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io 0x62 = 0x330
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irq 0x70 = 9
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end
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device pnp 2e.8 on # GPIO2
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# all default
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end
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device pnp 2e.9 on # GPIO3/4
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irq 0x30 = 0x03 # does this work?
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irq 0xf0 = 0xfb # set inputs/outputs
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irq 0xf1 = 0x66
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end
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device pnp 2e.a off # ACPI
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end
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device pnp 2e.b on # HWM
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io 0x60 = 0xa00
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irq 0x70 = 0
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end
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end
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chip superio/winbond/w83627thg
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device pnp 4e.0 off # Floppy
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end
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device pnp 4e.1 off # Parport
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end
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device pnp 4e.2 on # COM3
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io 0x60 = 0x3e8
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irq 0x70 = 11
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end
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device pnp 4e.3 on # COM4
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io 0x60 = 0x2e8
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irq 0x70 = 10
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end
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device pnp 4e.5 off # Keyboard
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end
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device pnp 4e.7 off # GPIO1, GAME, MIDI
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end
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device pnp 4e.8 off # GPIO2
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end
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device pnp 4e.9 off # GPIO3/4
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end
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device pnp 4e.a off # ACPI
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end
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device pnp 4e.b off # HWM
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end
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end
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end
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#device pci 1f.1 off end # IDE
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device pci 1f.2 on end # SATA
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device pci 1f.3 on end # SMBus
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#device pci 1f.4 off end # Realtek ID Codec
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end
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end
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end
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