a86a1837d2
This file had the memory regions applicable to ipq806x. Update the regions as applicable to ipq40xx. BUG=chrome-os-partner:49249 TEST=Able to boot on DK04 board BRANCH=none Change-Id: I0d782eb70fd62c6bf92f9fac39d2e42e9af82012 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e6a088c2666cf5be52358bb4271b45cb65d11f7c Original-Change-Id: I4fb3ca7fb168813d8871bfb87d475fd09d1a9d97 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333310 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14670 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
86 lines
2.6 KiB
C
86 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <symbols.h>
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#include <soc/ipq_uart.h>
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typedef struct {
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uint8_t hlos1[112 * MiB], /* <-- 0x80000000 */
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appsbl[4 * MiB], /* <-- 0x87000000 */
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sbl[1 * MiB], /* <-- 0x87400000 */
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rsvd[11 * MiB], /* <-- 0x87500000 */
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hlos2[128 * MiB]; /* <-- 0x88000000 */
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} ipq_mem_map_t;
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#define LINUX_REGION1_START ((uintptr_t)(ipq_mem_map->hlos1))
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#define LINUX_REGION1_START_KB (LINUX_REGION1_START / KiB)
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#define LINUX_REGION1_SIZE (sizeof(ipq_mem_map->hlos1) + \
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sizeof(ipq_mem_map->appsbl) + \
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sizeof(ipq_mem_map->sbl))
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#define LINUX_REGION1_SIZE_KB (LINUX_REGION1_SIZE / KiB)
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#define RESERVED_START ((uintptr_t)(ipq_mem_map->rsvd))
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#define RESERVED_START_KB (RESERVED_START / KiB)
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#define RESERVED_SIZE (sizeof(ipq_mem_map->rsvd))
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#define RESERVED_SIZE_KB (RESERVED_SIZE / KiB)
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/* xxx_SIZE defines not needed since it goes till end of memory */
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#define LINUX_REGION2_START ((uintptr_t)(ipq_mem_map->hlos2))
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#define LINUX_REGION2_START_KB (LINUX_REGION2_START / KiB)
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static void soc_read_resources(device_t dev)
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{
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ipq_mem_map_t *ipq_mem_map = ((ipq_mem_map_t *)_dram);
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ram_resource(dev, 0, LINUX_REGION1_START_KB, LINUX_REGION1_SIZE_KB);
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reserved_ram_resource(dev, 1, RESERVED_START_KB, RESERVED_SIZE_KB);
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/* 0x88000000 to end, is the second region for Linux */
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ram_resource(dev, 2, LINUX_REGION2_START_KB,
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(CONFIG_DRAM_SIZE_MB * KiB) -
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LINUX_REGION1_SIZE_KB - RESERVED_SIZE_KB);
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}
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static void soc_init(device_t dev)
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{
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/*
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* Do this in case console is not enabled: kernel's earlyprintk()
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* should work no matter what the firmware console configuration is.
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*/
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ipq40xx_uart_init();
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printk(BIOS_INFO, "CPU: QCA 40xx\n");
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}
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static struct device_operations soc_ops = {
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.read_resources = soc_read_resources,
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.init = soc_init,
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};
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static void enable_soc_dev(device_t dev)
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{
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dev->ops = &soc_ops;
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}
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struct chip_operations soc_qualcomm_ipq40xx_ops = {
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CHIP_NAME("SOC QCA 40xx")
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.enable_dev = enable_soc_dev,
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};
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