a8aef3acbc
Most devices do not use SPI before they initialize CBMEM. This change initializes spi_flash in the CBMEM_INIT_HOOK to initialize the postram cbfs cache so it is not overwritten when boot_device_init is called later. BUG=chromium:210230 BRANCH=none TEST=confirm that the first cbfs access can occur before RAM initialized and after on panther and jerry. Change-Id: If3b6efc04082190e81c3773c0d3ce116bb12421f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ab242786a16eba7fb423694f6b266e27d7660ec Original-Change-Id: I5f884b473e51e6813fdd726bba06b56baf3841b0 Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/314311 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12601 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
161 lines
4.6 KiB
C
161 lines
4.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This file contains macro definitions for memlayout.ld linker scripts. */
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#ifndef __MEMLAYOUT_H
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#define __MEMLAYOUT_H
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#include <rules.h>
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#include <arch/memlayout.h>
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/* Macros that the architecture can override. */
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#ifndef ARCH_POINTER_ALIGN_SIZE
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#define ARCH_POINTER_ALIGN_SIZE 8
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#endif
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#ifndef ARCH_CACHELINE_ALIGN_SIZE
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#define ARCH_CACHELINE_ALIGN_SIZE 64
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#endif
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/* Default to data as well as bss. */
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#ifndef ARCH_STAGE_HAS_DATA_SECTION
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#define ARCH_STAGE_HAS_DATA_SECTION 1
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#endif
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#ifndef ARCH_STAGE_HAS_BSS_SECTION
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#define ARCH_STAGE_HAS_BSS_SECTION 1
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#endif
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/* Default is that currently ramstage, smm, and rmodules have a heap. */
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#ifndef ARCH_STAGE_HAS_HEAP_SECTION
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#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE)
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#endif
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#define STR(x) #x
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#define ALIGN_COUNTER(align) \
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. = ALIGN(align);
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#define SET_COUNTER(name, addr) \
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_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
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. = addr;
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#define SYMBOL(name, addr) \
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SET_COUNTER(name, addr) \
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_##name = .;
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#define REGION(name, addr, size, expected_align) \
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SYMBOL(name, addr) \
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_ = ASSERT(. == ALIGN(expected_align), \
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STR(name must be aligned to expected_align!)); \
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SYMBOL(e##name, addr + size)
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/* Declare according to SRAM/DRAM ranges in SoC hardware-defined address map. */
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#define SRAM_START(addr) SYMBOL(sram, addr)
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#define SRAM_END(addr) SYMBOL(esram, addr)
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#define DRAM_START(addr) SYMBOL(dram, addr)
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#define TIMESTAMP(addr, size) \
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REGION(timestamp, addr, size, 8)
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#define PRERAM_CBMEM_CONSOLE(addr, size) \
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REGION(preram_cbmem_console, addr, size, 4)
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/* Use either CBFS_CACHE (unified) or both (PRERAM|POSTRAM)_CBFS_CACHE */
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#define CBFS_CACHE(addr, size) REGION(cbfs_cache, addr, size, 4)
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#if ENV_ROMSTAGE
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#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
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#define POSTRAM_CBFS_CACHE(addr, size) \
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REGION(postram_cbfs_cache, addr, size, 4)
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#elif defined(__PRE_RAM__)
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#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
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#define POSTRAM_CBFS_CACHE(addr, size) \
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REGION(unused_cbfs_cache, addr, size, 4)
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#else
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#define PRERAM_CBFS_CACHE(addr, size) \
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REGION(unused_cbfs_cache, addr, size, 4)
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#define POSTRAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
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#endif
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/* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
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#if ENV_BOOTBLOCK
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#define BOOTBLOCK(addr, sz) \
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SET_COUNTER(bootblock, addr) \
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_ = ASSERT(_eprogram - _program <= sz, \
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STR(Bootblock exceeded its allotted size! (sz))); \
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INCLUDE "lib/program.bootblock.ld"
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#else
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#define BOOTBLOCK(addr, sz) \
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SET_COUNTER(bootblock, addr) \
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. += sz;
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#endif
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#if ENV_ROMSTAGE
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#define ROMSTAGE(addr, sz) \
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SET_COUNTER(romstage, addr) \
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_ = ASSERT(_eprogram - _program <= sz, \
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STR(Romstage exceeded its allotted size! (sz))); \
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INCLUDE "lib/program.romstage.ld"
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#else
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#define ROMSTAGE(addr, sz) \
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SET_COUNTER(romstage, addr) \
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. += sz;
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#endif
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#if ENV_RAMSTAGE
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#define RAMSTAGE(addr, sz) \
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SET_COUNTER(ramstage, addr) \
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_ = ASSERT(_eprogram - _program <= sz, \
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STR(Ramstage exceeded its allotted size! (sz))); \
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INCLUDE "lib/program.ramstage.ld"
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#else
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#define RAMSTAGE(addr, sz) \
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SET_COUNTER(ramstage, addr) \
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. += sz;
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#endif
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/* Careful: required work buffer size depends on RW properties such as key size
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* and algorithm -- what works for you might stop working after an update. Do
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* NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
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#define VBOOT2_WORK(addr, size) \
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REGION(vboot2_work, addr, size, 16) \
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_ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
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#if ENV_VERSTAGE
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#define VERSTAGE(addr, sz) \
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SET_COUNTER(verstage, addr) \
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_ = ASSERT(_eprogram - _program <= sz, \
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STR(Verstage exceeded its allotted size! (sz))); \
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INCLUDE "lib/program.verstage.ld"
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#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size)
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#else
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#define VERSTAGE(addr, sz) \
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SET_COUNTER(verstage, addr) \
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. += sz;
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#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
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#endif
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#define WATCHDOG_TOMBSTONE(addr, size) \
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REGION(watchdog_tombstone, addr, size, 4) \
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_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
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#endif /* __MEMLAYOUT_H */
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