90176c56f4
Add a driver for systems with NVIDIA Optimus (hybrid) graphics using GC6 3.0. The driver provides ACPI support for dynamically powering on and off the GPU, and a function for enabling the GPU power in romstage. Tested on system76/gaze15. Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
203 lines
3.2 KiB
Plaintext
203 lines
3.2 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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Device (\_SB.PCI0.PEGP) {
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Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
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PowerResource (PWRR, 0, 0) {
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Name (_STA, 1)
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Method (_ON) {
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Debug = "PEGP.PWRR._ON"
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If (_STA != 1) {
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\_SB.PCI0.PEGP.DEV0._ON ()
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_STA = 1
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}
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}
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Method (_OFF) {
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Debug = "PEGP.PWRR._OFF"
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If (_STA != 0) {
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\_SB.PCI0.PEGP.DEV0._OFF ()
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_STA = 0
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}
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}
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}
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Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
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Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
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Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
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}
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Device (\_SB.PCI0.PEGP.DEV0) {
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Name(_ADR, 0x00000000)
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Name (_STA, 0xF)
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Name (LTRE, 0)
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// Memory mapped PCI express registers
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// Not sure what this stuff is, but it is used to get into GC6
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// TODO: use GPU config to generate address
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OperationRegion (RPCX, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0x8000, 0x1000)
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Field (RPCX, ByteAcc, NoLock, Preserve) {
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PVID, 16,
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PDID, 16,
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CMDR, 8,
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Offset (0x19),
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PRBN, 8,
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Offset (0x84),
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D0ST, 2,
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Offset (0xAA),
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CEDR, 1,
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Offset (0xAC),
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, 4,
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CMLW, 6,
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Offset (0xB0),
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ASPM, 2,
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, 2,
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P0LD, 1,
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RTLK, 1,
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Offset (0xC9),
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, 2,
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LREN, 1,
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Offset (0x11A),
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, 1,
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VCNP, 1,
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Offset (0x214),
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Offset (0x216),
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P0LS, 4,
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Offset (0x248),
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, 7,
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Q0L2, 1,
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Q0L0, 1,
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Offset (0x504),
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Offset (0x506),
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PCFG, 2,
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Offset (0x508),
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TREN, 1,
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Offset (0xC20),
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, 4,
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P0AP, 2,
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Offset (0xC38),
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, 3,
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P0RM, 1,
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Offset (0xC74),
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P0LT, 4,
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Offset (0xD0C),
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, 20,
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LREV, 1
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}
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Method (_ON) {
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Debug = "PEGP.DEV0._ON"
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If (_STA != 0xF) {
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Debug = " If DGPU_PWR_EN low"
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If (! GTXS (DGPU_PWR_EN)) {
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Debug = " DGPU_PWR_EN high"
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STXS (DGPU_PWR_EN)
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Debug = " Sleep 16"
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Sleep (16)
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}
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Debug = " DGPU_RST_N high"
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STXS(DGPU_RST_N)
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Debug = " Sleep 10"
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Sleep (10)
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Debug = " Q0L0 = 1"
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Q0L0 = 1
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Debug = " Sleep 16"
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Sleep (16)
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Debug = " While Q0L0"
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Local0 = 0
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While (Q0L0) {
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If ((Local0 > 4)) {
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Debug = " While Q0L0 timeout"
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Break
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}
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Sleep (16)
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Local0++
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}
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Debug = " P0RM = 0"
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P0RM = 0
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Debug = " P0AP = 0"
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P0AP = 0
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Debug = Concatenate(" LREN = ", ToHexString(LTRE))
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LREN = LTRE
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Debug = " CEDR = 1"
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CEDR = 1
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Debug = " CMDR |= 7"
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CMDR |= 7
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Debug = " _STA = 0xF"
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_STA = 0xF
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}
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}
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Method (_OFF) {
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Debug = "PEGP.DEV0._OFF"
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If (_STA != 0x5) {
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Debug = Concatenate(" LTRE = ", ToHexString(LREN))
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LTRE = LREN
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Debug = " Q0L2 = 1"
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Q0L2 = 1
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Debug = " Sleep 16"
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Sleep (16)
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Debug = " While Q0L2"
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Local0 = Zero
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While (Q0L2) {
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If ((Local0 > 4)) {
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Debug = " While Q0L2 timeout"
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Break
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}
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Sleep (16)
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Local0++
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}
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Debug = " P0RM = 1"
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P0RM = 1
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Debug = " P0AP = 3"
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P0AP = 3
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Debug = " Sleep 10"
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Sleep (10)
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Debug = " DGPU_RST_N low"
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CTXS(DGPU_RST_N)
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Debug = " While DGPU_GC6 low"
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Local0 = Zero
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While (! GRXS(DGPU_GC6)) {
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If ((Local0 > 4)) {
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Debug = " While DGPU_GC6 low timeout"
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Debug = " DGPU_PWR_EN low"
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CTXS (DGPU_PWR_EN)
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Break
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}
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Sleep (16)
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Local0++
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}
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Debug = " _STA = 0x5"
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_STA = 0x5
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}
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}
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}
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