a8d7c043f6
To have the new AMD Sabrina SoC code tested, add the AMD Chausie mainboard as a copy of Majolica. This patch also changes the name from Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC and comments out the APCB_SOURCES since those aren't available in the 3rdparty/blobs repository yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
35 lines
524 B
Plaintext
35 lines
524 B
Plaintext
FLASH@0xFF000000 16M {
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SI_BIOS {
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EC 128K
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RW_MRC_CACHE(PRESERVE) 64K
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RW_SECTION_A 3M {
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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RW_FWID_A 256
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}
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RW_SECTION_B 3M {
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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RW_FWID_B 256
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}
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RW_ELOG(PRESERVE) 4K
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RW_SHARED 16K {
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SHARED_DATA 8K
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VBLOCK_DEV 8K
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}
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RW_VPD(PRESERVE) 8K
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RW_NVRAM(PRESERVE) 20K
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SMMSTORE(PRESERVE) 4K
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RW_LEGACY(CBFS)
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WP_RO@8M 8M {
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RO_VPD(PRESERVE) 16K
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RO_SECTION {
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FMAP 2K
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RO_FRID 64
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GBB@4K 448K
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COREBOOT(CBFS)
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}
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}
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}
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}
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