a8df6cff16
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I166dbebf0eaf9fe0454145d4d48a0622743916fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
127 lines
3.4 KiB
C
127 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
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#define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
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#define DEFAULT_HECIBAR ((u8 *)0xfed17000)
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/*
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* D1:F0 PEG
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*/
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#define PEG_CAP 0xa2
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#define SLOTCAP 0xb4
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#define PEGLC 0xec
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#define D1F0_VCCAP 0x104
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#define D1F0_VC0RCTL 0x114
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/* Chipset types */
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#define IRONLAKE_MOBILE 0
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#define IRONLAKE_DESKTOP 1
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#define IRONLAKE_SERVER 2
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#include "memmap.h"
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#define QUICKPATH_BUS (CONFIG_MMCONF_BUS_NUMBER - 1)
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#include <southbridge/intel/ibexpeak/pch.h>
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/* Everything below this line is ignored in the DSDT */
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#ifndef __ACPI__
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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#include "registers/host_bridge.h"
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/*
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* Generic Non-Core Registers
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*/
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#define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0)
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#define MAX_RTIDS 0x60
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#define DESIRED_CORES 0x80
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#define MIRROR_PORT_CTL 0xd0
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/*
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* SAD - System Address Decoder
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*/
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#define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1)
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#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */
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#define QPD0F1_SMRAM 0x4d /* System Management RAM Control */
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#define SAD_PCIEXBAR 0x50
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#define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */
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#define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */
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/*
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* QPI Link 0
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*/
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#define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0)
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#define QPI_QPILCP 0x40 /* QPI Link Capability */
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#define QPI_QPILCL 0x48 /* QPI Link Control */
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#define QPI_QPILS 0x50 /* QPI Link Status */
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#define QPI_DEF_RMT_VN_CREDITS 0x58 /* Default Available Remote Credits */
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/*
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* QPI Physical Layer 0
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*/
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#define QPI_PHY_0 PCI_DEV(QUICKPATH_BUS, 2, 1)
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#define QPI_PLL_STATUS 0x50
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#define QPI_PLL_RATIO 0x54
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#define QPI_PHY_CAPABILITY 0x68 /* QPI Phys. Layer Capability */
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#define QPI_PHY_CONTROL 0x6c /* QPI Phys. Layer Control */
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#define QPI_PHY_INIT_STATUS 0x80 /* QPI Phys. Layer Initialization Status */
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#define QPI_PHY_PRIM_TIMEOUT 0x94 /* QPI Phys. Layer Primary Timeout Value */
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#define QPI_PHY_PWR_MGMT 0xd0 /* QPI Phys. Layer Power Management */
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#define QPI_PHY_EP_SELECT 0xe0 /* QPI Phys. Layer Electrical Parameter Select */
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#define QPI_PHY_EP_MCTR 0xf4 /* QPI Phys. Layer Electrical Parameter Misc. Control */
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/* Device 0:2.0 PCI configuration space (Graphics Device) */
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#define MSAC 0x62 /* Multi Size Aperture Control */
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/*
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* MCHBAR
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*/
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#include <northbridge/intel/common/fixed_bars.h>
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#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
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#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
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#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
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#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
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#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or))
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#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or))
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#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
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#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
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#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
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/*
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* EPBAR - Egress Port Root Complex Register Block
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*/
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#include "registers/epbar.h"
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/*
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* DMIBAR
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*/
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#include "registers/dmibar.h"
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#ifndef __ASSEMBLER__
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void intel_ironlake_finalize_smm(void);
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int bridge_silicon_revision(void);
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void ironlake_early_initialization(int chipset_type);
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void ironlake_late_initialization(void);
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void mainboard_pre_raminit(void);
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void mainboard_get_spd_map(u8 *spd_addrmap);
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#endif
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#endif
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#endif /* __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ */
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