a8e1168064
be required for a series of later patches. Roughly it contains: * fixed SMBus driver (was not compiled in before) * fixed S-ATA/P-ATA combination * Added warnings to drivers being called with a NULL dev->chip_info * Set subsystem ids for those boards that have none specified in Options.lb * Fix license headers. The code was originally released under GPL v2 but some files sneaked in with a v2 or later header. * some attempts to fix azalia/Intel HDA.. not working yet * clean up and fix pci bridge handling code * Add Config based GPI handling to LPC driver * Add HPET enable function * Enable clock gating where appropriate * first attempt at USB debug console support (not working yet) * Add required options to kontron board * many other minor changes Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
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* Copyright (C) 2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/smbus_def.h>
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static void smbus_delay(void)
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{
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inb(0x80);
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}
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static int smbus_wait_until_ready(u16 smbus_base)
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{
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unsigned loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while (byte & 1);
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return loops ? 0 : -1;
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}
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static int smbus_wait_until_done(u16 smbus_base)
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{
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unsigned loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
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return loops ? 0 : -1;
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}
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static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
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{
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unsigned char global_status_register;
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unsigned char byte;
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if (smbus_wait_until_ready(smbus_base) < 0) {
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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/* Setup transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
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/* Set the device I'm talking too */
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outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(0, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_until_done(smbus_base) < 0) {
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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}
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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global_status_register &= ~(3 << 5);
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/* Read results of transaction */
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byte = inb(smbus_base + SMBHSTDAT0);
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if (global_status_register != (1 << 1)) {
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return SMBUS_ERROR;
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}
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return byte;
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}
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