a9473ecbb1
Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
302 lines
8.4 KiB
C
302 lines
8.4 KiB
C
#ifndef CPU_X86_MSR_H
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#define CPU_X86_MSR_H
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/* Intel SDM: Table 2-1
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* IA-32 architectural MSR: Extended Feature Enable Register
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*
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* AMD64 Programmers Manual vol2 Revision 3.30 and/or the device's BKDG
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*/
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#define IA32_EFER 0xC0000080
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#define EFER_NXE (1 << 11)
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#define EFER_LMA (1 << 10)
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#define EFER_LME (1 << 8)
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#define EFER_SCE (1 << 0)
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/* Page attribute type MSR */
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#define TSC_MSR 0x10
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#define IA32_PLATFORM_ID 0x17
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#define IA32_FEATURE_CONTROL 0x3a
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#define FEATURE_CONTROL_LOCK_BIT (1 << 0)
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#define FEATURE_ENABLE_VMX (1 << 2)
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#define SMRR_ENABLE (1 << 3)
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#define CPUID_VMX (1 << 5)
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#define CPUID_SMX (1 << 6)
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#define SGX_GLOBAL_ENABLE (1 << 18)
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#define PLATFORM_INFO_SET_TDP (1 << 29)
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#define IA32_BIOS_UPDT_TRIG 0x79
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#define IA32_BIOS_SIGN_ID 0x8b
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#define IA32_MPERF 0xe7
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#define IA32_APERF 0xe8
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#define IA32_MCG_CAP 0x179
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#define MCG_CTL_P (1 << 3)
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#define MCA_BANKS_MASK 0xff
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#define IA32_PERF_STATUS 0x198
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#define IA32_PERF_CTL 0x199
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#define IA32_THERM_INTERRUPT 0x19b
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#define IA32_MISC_ENABLE 0x1a0
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#define IA32_ENERGY_PERF_BIAS 0x1b0
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#define ENERGY_POLICY_PERFORMANCE 0
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#define ENERGY_POLICY_NORMAL 6
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#define ENERGY_POLICY_POWERSAVE 15
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#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
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#define IA32_PLATFORM_DCA_CAP 0x1f8
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#define IA32_PAT 0x277
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#define IA32_MC0_CTL 0x400
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#define IA32_MC0_STATUS 0x401
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#define MCA_STATUS_HI_VAL (1UL << (63 - 32))
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#define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32))
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#define MCA_STATUS_HI_UC (1UL << (61 - 32))
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#define MCA_STATUS_HI_EN (1UL << (60 - 32))
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#define MCA_STATUS_HI_MISCV (1UL << (59 - 32))
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#define MCA_STATUS_HI_ADDRV (1UL << (58 - 32))
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#define MCA_STATUS_HI_PCC (1UL << (57 - 32))
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#define MCA_STATUS_HI_COREID_VAL (1UL << (56 - 32))
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#define MCA_STATUS_HI_CECC (1UL << (46 - 32))
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#define MCA_STATUS_HI_UECC (1UL << (45 - 32))
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#define MCA_STATUS_HI_DEFERRED (1UL << (44 - 32))
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#define MCA_STATUS_HI_POISON (1UL << (43 - 32))
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#define MCA_STATUS_HI_SUBLINK (1UL << (41 - 32))
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#define MCA_STATUS_HI_ERRCOREID_MASK (0xf << 0)
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#define MCA_STATUS_LO_ERRCODE_EXT_SH 16
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#define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
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#define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
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#define MC0_ADDR 0x402
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#define MC0_MISC 0x403
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#define MC0_CTL_MASK 0xC0010044
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#define IA32_PM_ENABLE 0x770
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#define IA32_HWP_CAPABILITIES 0x771
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#define IA32_HWP_REQUEST 0x774
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#define IA32_HWP_STATUS 0x777
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#define IA32_PQR_ASSOC 0xc8f
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/* MSR bits 33:32 encode slot number 0-3 */
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#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)
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#define IA32_L3_MASK_1 0xc91
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#define IA32_L3_MASK_2 0xc92
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#ifndef __ASSEMBLER__
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#include <types.h>
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#if defined(__ROMCC__)
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typedef __builtin_msr_t msr_t;
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static msr_t rdmsr(unsigned long index)
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{
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return __builtin_rdmsr(index);
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}
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static void wrmsr(unsigned long index, msr_t msr)
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{
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__builtin_wrmsr(index, msr.lo, msr.hi);
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}
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#else
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typedef struct msr_struct {
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unsigned int lo;
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unsigned int hi;
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} msr_t;
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typedef struct msrinit_struct {
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unsigned int index;
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msr_t msr;
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} msrinit_t;
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#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
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msr_t soc_msr_read(unsigned int index);
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void soc_msr_write(unsigned int index, msr_t msr);
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/* Handle MSR references in the other source code */
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static __always_inline msr_t rdmsr(unsigned int index)
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{
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return soc_msr_read(index);
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}
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static __always_inline void wrmsr(unsigned int index, msr_t msr)
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{
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soc_msr_write(index, msr);
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}
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#else /* CONFIG_SOC_SETS_MSRS */
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/* The following functions require the __always_inline due to AMD
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* function STOP_CAR_AND_CPU that disables cache as
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* RAM, the cache as RAM stack can no longer be used. Called
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* functions must be inlined to avoid stack usage. Also, the
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* compiler must keep local variables register based and not
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* allocated them from the stack. With gcc 4.5.0, some functions
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* declared as inline are not being inlined. This patch forces
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* these functions to always be inlined by adding the qualifier
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* __always_inline to their declaration.
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*/
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static __always_inline msr_t rdmsr(unsigned int index)
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{
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msr_t result;
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__asm__ __volatile__ (
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"rdmsr"
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: "=a" (result.lo), "=d" (result.hi)
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: "c" (index)
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);
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return result;
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}
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static __always_inline void wrmsr(unsigned int index, msr_t msr)
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{
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__asm__ __volatile__ (
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"wrmsr"
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: /* No outputs */
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: "c" (index), "a" (msr.lo), "d" (msr.hi)
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);
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}
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#endif /* CONFIG_SOC_SETS_MSRS */
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#endif /* __ROMCC__ */
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/* Helpers for interpreting MC[i]_STATUS */
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static inline int mca_valid(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_VAL);
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}
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static inline int mca_over(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_OVERFLOW);
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}
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static inline int mca_uc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_UC);
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}
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static inline int mca_en(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_EN);
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}
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static inline int mca_miscv(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_MISCV);
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}
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static inline int mca_addrv(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_ADDRV);
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}
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static inline int mca_pcc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_PCC);
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}
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static inline int mca_idv(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);
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}
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static inline int mca_cecc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_CECC);
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}
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static inline int mca_uecc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_UECC);
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}
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static inline int mca_defd(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_DEFERRED);
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}
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static inline int mca_poison(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_POISON);
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}
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static inline int mca_sublink(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_SUBLINK);
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}
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static inline uint16_t mca_err_code(msr_t reg)
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{
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return reg.lo & MCA_STATUS_LO_ERRCODE_MASK;
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}
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static inline uint16_t mca_err_extcode(msr_t reg)
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{
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return reg.lo & MCA_STATUS_LO_ERRCODE_EXT_MASK;
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}
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/* Machine Check errors may be categorized by type, as determined by the
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* Error Code field of MC[i]_STATUS. The definitions below can typically
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* be found by searching the BKDG for a table called "Error Code Types".
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*/
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/* TLB Errors 0000 0000 0001 TTLL */
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#define MCA_ERRCODE_TLB_DETECT 0xfff0
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#define MCA_ERRCODE_TLB_TT_SH 2 /* Transaction Type */
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#define MCA_ERRCODE_TLB_TT_MASK (0x3 << MCA_ERRCODE_TLB_TT_SH)
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#define MCA_ERRCODE_TLB_LL_SH 0 /* Cache Level */
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#define MCA_ERRCODE_TLB_LL_MASK (0x3 << MCA_ERRCODE_TLB_LL_SH)
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/* Memory Errors 0000 0001 RRRR TTLL */
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#define MCA_ERRCODE_MEM_DETECT 0xff00
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#define MCA_ERRCODE_MEM_RRRR_SH 4 /* Memory Transaction Type */
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#define MCA_ERRCODE_MEM_RRRR_MASK (0xf << MCA_ERRCODE_MEM_RRRR_MASK)
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#define MCA_ERRCODE_MEM_TT_SH 2 /* Transaction Type */
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#define MCA_ERRCODE_MEM_TT_MASK (0x3 << MCA_ERRCODE_MEM_TT_SH)
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#define MCA_ERRCODE_MEM_LL_SH 0 /* Cache Level */
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#define MCA_ERRCODE_MEM_LL_MASK (0x3 << MCA_ERRCODE_MEM_LL_SH)
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/* Bus Errors 0000 1PPT RRRR IILL */
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#define MCA_ERRCODE_BUS_DETECT 0xf800
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#define MCA_ERRCODE_BUS_PP_SH 9 /* Participation Processor */
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#define MCA_ERRCODE_BUS_PP_MASK (0x3 << MCA_ERRCODE_BUS_PP_SH)
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#define MCA_ERRCODE_BUS_T_SH 8 /* Timeout */
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#define MCA_ERRCODE_BUS_T_MASK (0x1 << MCA_ERRCODE_BUS_T_SH)
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#define MCA_ERRCODE_BUS_RRRR_SH 4 /* Memory Transaction Type */
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#define MCA_ERRCODE_BUS_RRRR_MASK (0xf << MCA_ERRCODE_BUS_RRRR_SH)
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#define MCA_ERRCODE_BUS_II_SH 2 /* Memory or IO */
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#define MCA_ERRCODE_BUS_II_MASK (0x3 << MCA_ERRCODE_BUS_II_SH)
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#define MCA_ERRCODE_BUS_LL_SH 0 /* Cache Level */
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#define MCA_ERRCODE_BUS_LL_MASK (0x3 << MCA_ERRCODE_BUS_LL_SH)
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/* Int. Unclassified Errors 0000 01UU 0000 0000 */
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#define MCA_ERRCODE_INT_DETECT 0xfc00
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#define MCA_ERRCODE_INT_UU_SH 8 /* Internal Error Type */
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#define MCA_ERRCODE_INT_UU_MASK (0x3 << MCA_ERRCODE_INT_UU_SH)
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#define MCA_BANK_LS 0 /* Load-store, including DC */
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#define MCA_BANK_IF 1 /* Instruction Fetch, including IC */
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#define MCA_BANK_CU 2 /* Combined Unit, including L2 */
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/* bank 3 reserved */
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#define MCA_BANK_NB 4 /* Northbridge, including IO link */
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#define MCA_BANK_EX 5 /* Execution Unit */
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#define MCA_BANK_FP 6 /* Floating Point */
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enum mca_err_code_types {
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MCA_ERRTYPE_UNKNOWN,
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MCA_ERRTYPE_TLB,
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MCA_ERRTYPE_MEM,
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MCA_ERRTYPE_BUS,
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MCA_ERRTYPE_INT
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};
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static inline enum mca_err_code_types mca_err_type(msr_t reg)
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{
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uint16_t error = mca_err_code(reg);
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if (error & MCA_ERRCODE_BUS_DETECT) /* this order must be maintained */
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return MCA_ERRTYPE_BUS;
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if (error & MCA_ERRCODE_INT_DETECT)
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return MCA_ERRTYPE_INT;
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if (error & MCA_ERRCODE_MEM_DETECT)
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return MCA_ERRTYPE_MEM;
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if (error & MCA_ERRCODE_TLB_DETECT)
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return MCA_ERRTYPE_TLB;
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return MCA_ERRTYPE_UNKNOWN;
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}
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#endif /* __ASSEMBLER__ */
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#endif /* CPU_X86_MSR_H */
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