aa41f77397
Move the EC to a location that does not conflict with where the main CBFS is in the chromeos FMAP Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
95 lines
2.1 KiB
Plaintext
95 lines
2.1 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_AMD_CHAUSIE
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_RESUME
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select SOC_AMD_SABRINA
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select SOC_AMD_COMMON_BLOCK_USE_ESPI
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select AMD_SOC_CONSOLE_UART
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select MAINBOARD_HAS_CHROMEOS
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config FMDFILE
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default "src/mainboard/amd/chausie/chromeos.fmd" if CHROMEOS
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default "src/mainboard/amd/chausie/board.fmd"
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config MAINBOARD_DIR
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default "amd/chausie"
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config MAINBOARD_PART_NUMBER
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default "CHAUSIE"
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config AMD_FWM_POSITION_INDEX
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int
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default 3 if CHROMEOS
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help
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TODO: might need to be adapted for better placement of files in cbfs
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config CHAUSIE_HAVE_MCHP_FW
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bool "Have Microchip EC firmware?"
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default n
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config CHAUSIE_MCHP_SIG_FILE
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string
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depends on CHAUSIE_HAVE_MCHP_FW
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default "3rdparty/blobs/mainboard/amd/chausie/EC_chausie_sig.bin"
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help
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The EC sig blob is the first 4kBytes of the firmware image.
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The first 4 bytes form a pointer (with CRC) to where the EC firmware
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is located
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config CHAUSIE_MCHP_FW_FILE
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string
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depends on CHAUSIE_HAVE_MCHP_FW
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default "3rdparty/blobs/mainboard/amd/chausie/EC_chausie.bin"
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help
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The EC firmware blob is at the CHAUSIE_MCHP_FW_OFFSET offset of the
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firmware image.
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config CHAUSIE_MCHP_FW_OFFSET
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hex
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depends on CHAUSIE_HAVE_MCHP_FW
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default 0xB80000
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help
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The EC firmware blob defaults to the 4MByte offset of the firmware
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image. If this offset needs to change, a new signature block must be
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generated with the updated offset.
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config VBOOT
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select VBOOT_NO_BOARD_SUPPORT
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select VBOOT_SEPARATE_VERSTAGE
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select VBOOT_STARTS_IN_BOOTBLOCK
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config VBOOT_VBNV_OFFSET
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hex
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default 0x2A
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config CHROMEOS
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# Use default libpayload config
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select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
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if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig
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config EFS_SPI_READ_MODE
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default 3 # Quad IO (1-1-4)
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config EFS_SPI_SPEED
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default 0 # 66MHz
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config EFS_SPI_MICRON_FLAG
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default 0
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config NORMAL_READ_SPI_SPEED
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default 1 # 33MHz
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config ALT_SPI_SPEED
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default 1 # 33MHz
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config TPM_SPI_SPEED
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default 1 # 33MHz
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endif # !EM100
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endif # BOARD_AMD_CHAUSIE
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