aa49608a2b
Power limits (PL1 and PL2) depend on the specific SKU of the CPU. By expanding the SoC chip config power_limits_config member to an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the appropriate power limits are applied. Using this the correct set of power limits are being selected from the array based on system agent PCI ID. Based on this, chipset.cb file contains the set of power limits being used by varieties of ADL boards. These power limit values are as per document 619501. BUG=None BRANCH=None TEST=Built and verified the following console output on below boards On adlrvp (482): CPU PL1 = 28 Watts CPU PL2 = 64 Watts On adlrvp (682): CPU PL1 = 45 Watts CPU PL2 = 115 Watts On brya (282): CPU PL1 = 15 Watts CPU PL2 = 55 Watts Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
362 lines
9.6 KiB
Plaintext
362 lines
9.6 KiB
Plaintext
chip soc/intel/alderlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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# Enable HECI1 interface
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register "HeciEnabled" = "1"
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# FSP configuration
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# Enable CNVi BT
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register "CnviBtCore" = "true"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2
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register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# This disabled autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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# Enable PCH PCIE RP 5 using CLK 2
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable PCH PCIE RP 6 using CLK 5
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable PCH PCIE RP 8 using free running CLK (0x80)
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# Clock source is shared with LAN and hence marked as free running.
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register "pch_pcie_rp[PCH_RP(8)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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}"
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register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
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# Enable PCH PCIE RP 9 using CLK 1
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable PCH PCIE RP 11 for optane
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register "pch_pcie_rp[PCH_RP(11)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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}"
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# Hybrid storage mode
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register "HybridStorageMode" = "1"
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# Enable CPU PCIE RP 1 using CLK 0
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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}"
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# Enable CPU PCIE RP 2 using CLK 3
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register "cpu_pcie_rp[CPU_RP(2)]" = "{
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.clk_req = 3,
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.clk_src = 3,
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}"
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# Enable CPU PCIE RP 3 using CLK 4
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register "cpu_pcie_rp[CPU_RP(3)]" = "{
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.clk_req = 4,
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.clk_src = 4,
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}"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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}"
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register "SataPortsDevSlp" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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}"
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# Enable EDP in PortA
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register "DdiPortAConfig" = "1"
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# Enable HDMI in Port B
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register "DdiPortBDdc" = "1"
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register "DdiPortBHpd" = "1"
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# TCSS USB3
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register "TcssAuxOri" = "0"
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register "s0ix_enable" = "1"
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register "dptf_enable" = "1"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoPci,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoGSpiCsState" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# HD Audio
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register "PchHdaDspEnable" = "1"
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register "PchHdaIDispLinkTmode" = "HDA_TMODE_4T"
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register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
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register "PchHdaIDispCodecEnable" = "1"
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register "CnviBtAudioOffload" = "true"
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# Intel Common SoC Config
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device ref pcie5 on end
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device ref igpu on end
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""Ambient""
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register "options.tsr[1].desc" = ""Battery""
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register "options.tsr[2].desc" = ""DDR""
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register "options.tsr[3].desc" = ""Skin""
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## Active Policy
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# TODO: below values are initial reference values only
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register "policies.active" = "{
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[0] = {
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.target = DPTF_CPU,
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.thresholds = {
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TEMP_PCT(95, 90),
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TEMP_PCT(90, 80),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_0,
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.thresholds = {
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TEMP_PCT(80, 90),
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TEMP_PCT(70, 80),
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}
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}
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}"
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## Passive Policy
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# TODO: below values are initial reference values only
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 10000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000),
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[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000),
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000),
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[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000),
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}"
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## Critical Policy
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# TODO: below values are initial reference values only
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
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[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
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}"
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## Power Limits Control
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 35000,
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.max_power = 45000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 56000,
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.max_power = 56000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 3000 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 90, 6700, 220, 2200, },
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[1] = { 80, 5800, 180, 1800, },
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[2] = { 70, 5000, 145, 1450, },
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[3] = { 60, 4900, 115, 1150, },
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[4] = { 50, 3838, 90, 900, },
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[5] = { 40, 2904, 55, 550, },
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[6] = { 30, 2337, 30, 300, },
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[7] = { 20, 1608, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 on end
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end
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end
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device ref ipu on end
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device ref pcie4_0 on end
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device ref pcie4_1 on end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp1 on end
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device ref tbt_pcie_rp2 on end
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device ref tbt_pcie_rp3 on end
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device ref crashlog off end
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device ref tcss_xhci on end
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device ref tcss_xdci on end
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device ref tcss_dma0 on end
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device ref tcss_dma1 on end
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device ref xhci on
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chip drivers/usb/acpi
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register "desc" = ""Root Hub""
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register "type" = "UPC_TYPE_HUB"
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port10 on end
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end
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end
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end
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end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref i2c0 on end
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device ref i2c1 on end
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device ref i2c2 on end
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device ref i2c3 on end
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device ref heci1 on end
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device ref sata on end
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device ref i2c5 on end
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device ref pcie_rp1 on end
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device ref pcie_rp3 on end # W/A to FSP issue
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device ref pcie_rp4 on end # W/A to FSP issue
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device ref pcie_rp5 on end
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device ref pcie_rp6 on end
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device ref pcie_rp8 on end
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device ref pcie_rp9 on end
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device ref pcie_rp11 on end
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device ref uart0 on end
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device ref gspi0 on end
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device ref p2sb on end
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device ref hda on
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chip drivers/intel/soundwire
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device generic 0 on
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chip drivers/soundwire/alc711
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# SoundWire Link 0 ID 1
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register "desc" = ""Headset Codec""
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device generic 0.1 on end
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end
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end
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end
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end
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device ref smbus on end
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end
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end
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