aa57187f82
Change-Id: I4cd9d22d2105c270a3d1e8a0be40b594c7c8b226 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37687 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
87 lines
2.5 KiB
C
87 lines
2.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <cpu/x86/lapic.h>
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#include <arch/acpi.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <cpu/x86/msr.h>
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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struct pei_data pei_data_template = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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.epbar = DEFAULT_EPBAR,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.smbusbar = SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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.hpet_address = CONFIG_HPET_ADDRESS,
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.rcba = (uintptr_t)DEFAULT_RCBABASE,
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.pmbase = DEFAULT_PMBASE,
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.gpiobase = DEFAULT_GPIOBASE,
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.thermalbase = 0xfed08000,
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.system_type = 0, // 0 Mobile, 1 Desktop/Server
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.spd_addresses = { 0xa0, 0x00,0xa2,0x00 },
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.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
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.ec_present = 1,
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.gbe_enable = 1,
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// 0 = leave channel enabled
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// 1 = disable dimm 0 on channel
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// 2 = disable dimm 1 on channel
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// 3 = disable dimm 0+1 on channel
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.dimm_channel0_disabled = 2,
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.dimm_channel1_disabled = 2,
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.max_ddr3_freq = 1333,
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.usb_port_config = {
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{ 1, 0, 0x0040 },
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{ 1, 1, 0x0080 },
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{ 1, 3, 0x0080 },
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{ 1, 3, 0x0080 },
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{ 1, 0, 0x0080 },
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{ 1, 0, 0x0080 },
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{ 1, 2, 0x0040 },
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{ 1, 2, 0x0040 },
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{ 1, 6, 0x0080 },
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{ 1, 5, 0x0080 },
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{ 1, 6, 0x0080 },
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{ 1, 6, 0x0080 },
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{ 1, 7, 0x0080 },
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{ 1, 6, 0x0080 },
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},
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};
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*pei_data = pei_data_template;
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}
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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read_spd (&spd[0], 0x50, id_only);
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read_spd (&spd[2], 0x51, id_only);
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}
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int mainboard_should_reset_usb(int s3resume)
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{
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return !s3resume;
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}
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