aa5ff5a0fc
Don't make the default paths to AMD blobs depend on USE_AMD_BLOBS. This way we get error messages about the missing files when the blobs repos aren't checked out. Change-Id: I754fdc5e1414c8a3dc88b364bcfbea9a26b59eb0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
404 lines
10 KiB
Plaintext
404 lines
10 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config SOC_AMD_STONEYRIDGE
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bool
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help
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AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh.
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if SOC_AMD_STONEYRIDGE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_ALL_STAGES_X86_32
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select X86_AMD_FIXED_MTRRS
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select ACPI_AMD_HARDWARE_SLEEP_VALUES
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select COLLECT_TIMESTAMPS_NO_TSC
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select DRIVERS_I2C_DESIGNWARE
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select GENERIC_GPIO_LIB
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select GENERIC_UDELAY
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select IOAPIC
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select HAVE_CF9_RESET
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select HAVE_USBDEBUG_OPTIONS
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select SOC_AMD_COMMON_BLOCK_SPI
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select TSC_SYNC_LFENCE
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select SOC_AMD_PI
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select SOC_AMD_COMMON
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select SOC_AMD_COMMON_BLOCK_IOMMU
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select SOC_AMD_COMMON_BLOCK_ACPIMMIO
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select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
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select SOC_AMD_COMMON_BLOCK_ACPI
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select SOC_AMD_COMMON_BLOCK_AOAC
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select SOC_AMD_COMMON_BLOCK_LPC
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_HDA
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select SOC_AMD_COMMON_BLOCK_SATA
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select SOC_AMD_COMMON_BLOCK_PI
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select SOC_AMD_COMMON_BLOCK_PSP_GEN1
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select SOC_AMD_COMMON_BLOCK_CAR
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select SOC_AMD_COMMON_BLOCK_S3
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select SOC_AMD_COMMON_BLOCK_SMBUS
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select SOC_AMD_COMMON_BLOCK_SMI
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select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select HAVE_SMI_HANDLER
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select SSE2
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select RTC
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select ACPI_NO_SMI_GNVS
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config AMD_APU_STONEYRIDGE
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bool
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help
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AMD Stoney Ridge APU
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config AMD_APU_PRAIRIEFALCON
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bool
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help
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AMD Embedded Prairie Falcon APU
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config AMD_APU_MERLINFALCON
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bool
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help
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AMD Embedded Merlin Falcon APU
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config AMD_APU_PKG_FP4
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bool
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help
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AMD FP4 package
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config AMD_APU_PKG_FT4
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bool
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help
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AMD FT4 package
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config AMD_SOC_PACKAGE
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string
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default "FP4" if AMD_APU_PKG_FP4
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default "FT4" if AMD_APU_PKG_FT4
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config VBOOT
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select VBOOT_SEPARATE_VERSTAGE
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select VBOOT_STARTS_IN_BOOTBLOCK
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select VBOOT_VBNV_CMOS
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select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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# TODO: Sync these with definitions in PI vendorcode.
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# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
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# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
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config DCACHE_RAM_BASE
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hex
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default 0x30000
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config DCACHE_RAM_SIZE
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hex
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default 0x10000
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0x1600
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help
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Increase this value if preram cbmem console is getting truncated
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config CPU_ADDR_BITS
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int
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default 48
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config BOTTOMIO_POSITION
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hex "Bottom of 32-bit IO space"
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default 0xD0000000
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help
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If PCI peripherals with big BARs are connected to the system
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the bottom of the IO must be decreased to allocate such
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devices.
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Declare the beginning of the 128MB-aligned MMIO region. This
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option is useful when PCI peripherals requesting large address
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ranges are present.
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config MMCONF_BASE_ADDRESS
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hex
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default 0xF8000000
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config MMCONF_BUS_NUMBER
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int
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default 64
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config VGA_BIOS_ID
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string
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default "1002,9874" if AMD_APU_MERLINFALCON
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default "1002,98e4"
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help
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The default VGA BIOS PCI vendor/device ID should be set to the
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result of the map_oprom_vendev() function in northbridge.c.
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config VGA_BIOS_FILE
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string
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default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON
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default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_PRAIRIEFALCON
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default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_STONEYRIDGE
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config S3_VGA_ROM_RUN
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bool
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default n
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config HEAP_SIZE
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hex
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default 0xc0000
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config EHCI_BAR
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hex
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default 0xfef00000
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config STONEYRIDGE_XHCI_ENABLE
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bool "Enable Stoney Ridge XHCI Controller"
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default y
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help
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The XHCI controller must be enabled and the XHCI firmware
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must be added in order to have USB 3.0 support configured
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by coreboot. The OS will be responsible for enabling the XHCI
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controller if the XHCI firmware is available but the
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XHCI controller is not enabled by coreboot.
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config STONEYRIDGE_XHCI_FWM
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bool "Add xhci firmware"
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default y
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help
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Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0
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config STONEYRIDGE_GEC_FWM
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bool
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default n
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help
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Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC.
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Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
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config STONEYRIDGE_XHCI_FWM_FILE
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string "XHCI firmware path and filename"
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default "3rdparty/amd_blobs/stoneyridge/xhci.bin"
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depends on STONEYRIDGE_XHCI_FWM
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config STONEYRIDGE_GEC_FWM_FILE
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string "GEC firmware path and filename"
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depends on STONEYRIDGE_GEC_FWM
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config AMDFW_CONFIG_FILE
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string
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string "AMD PSP Firmware config file"
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default "src/soc/amd/stoneyridge/fw_cz.cfg" if AMD_APU_MERLINFALCON
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default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_PRAIRIEFALCON
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default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_STONEYRIDGE
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config STONEYRIDGE_SATA_MODE
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int "SATA Mode"
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default 0
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range 0 6
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help
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Select the mode in which SATA should be driven.
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The default is NATIVE.
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0: NATIVE mode does not require a ROM.
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2: AHCI may work with or without AHCI ROM. It depends on the payload support.
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For example, seabios does not require the AHCI ROM.
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3: LEGACY IDE
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4: IDE to AHCI
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5: AHCI7804: ROM Required, and AMD driver required in the OS.
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6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
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comment "NATIVE"
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depends on STONEYRIDGE_SATA_MODE = 0
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comment "AHCI"
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depends on STONEYRIDGE_SATA_MODE = 2
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comment "LEGACY IDE"
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depends on STONEYRIDGE_SATA_MODE = 3
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comment "IDE to AHCI"
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depends on STONEYRIDGE_SATA_MODE = 4
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comment "AHCI7804"
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depends on STONEYRIDGE_SATA_MODE = 5
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comment "IDE to AHCI7804"
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depends on STONEYRIDGE_SATA_MODE = 6
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if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
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config AHCI_ROM_ID
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string "AHCI device PCI IDs"
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default "1022,7801" if STONEYRIDGE_SATA_MODE = 2
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default "1022,7804" if STONEYRIDGE_SATA_MODE = 5
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endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
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config STONEYRIDGE_LEGACY_FREE
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bool "System is legacy free"
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help
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Select y if there is no keyboard controller in the system.
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This sets variables in AGESA and ACPI.
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config SERIRQ_CONTINUOUS_MODE
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bool
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default n
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help
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Set this option to y for serial IRQ in continuous mode.
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Otherwise it is in quiet mode.
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config STONEYRIDGE_ACPI_IO_BASE
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hex
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default 0x400
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help
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Base address for the ACPI registers.
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This value must match the hardcoded value of AGESA.
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config STONEYRIDGE_UART
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bool "UART controller on Stoney Ridge"
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default n
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select DRIVERS_UART_8250MEM
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select DRIVERS_UART_8250MEM_32
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select NO_UART_ON_SUPERIO
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select UART_OVERRIDE_REFCLK
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help
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There are two UART controllers in Stoney Ridge.
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The UART registers are memory-mapped. UART
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controller 0 registers range from FEDC_6000h
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to FEDC_6FFFh. UART controller 1 registers
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range from FEDC_8000h to FEDC_8FFFh.
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config CONSOLE_UART_BASE_ADDRESS
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depends on CONSOLE_SERIAL
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hex
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default 0xfedc6000
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config SMM_TSEG_SIZE
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hex
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default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
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default 0x0
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config SMM_RESERVED_SIZE
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hex
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default 0x150000
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config SMM_MODULE_STACK_SIZE
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hex
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default 0x800
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config ACPI_CPU_STRING
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string
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default "\\_SB.P%03d"
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config ACPI_BERT
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bool "Build ACPI BERT Table"
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default y
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depends on HAVE_ACPI_TABLES
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help
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Report Machine Check errors identified in POST to the OS in an
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ACPI Boot Error Record Table. This option reserves an 8MB region
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for building the error structures.
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config USE_PSPSECUREOS
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bool "Include PSP SecureOS blobs in AMD firmware"
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default y
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help
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Include the PspSecureOs, PspTrustlet and TrustletKey binaries
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in the amdfw section.
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If unsure, answer 'y'
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config SOC_AMD_PSP_SELECTABLE_SMU_FW
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bool
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default y if AMD_APU_STONEYRIDGE
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help
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Some ST implementations allow storing SMU firmware into cbfs and
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calling the PSP to load the blobs at the proper time.
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Merlin Falcon does not support it. If you are using 00670F00 SOC,
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ask your AMD representative if it supports it or not.
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config SOC_AMD_SMU_FANLESS
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bool
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depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
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default n if SOC_AMD_SMU_NOTFANLESS
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default y
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config SOC_AMD_SMU_FANNED
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bool
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depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
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default n
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select SOC_AMD_SMU_NOTFANLESS
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config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use
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bool
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depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
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config AMDFW_OUTSIDE_CBFS
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bool "The AMD firmware is outside CBFS"
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default n
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help
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The AMDFW (PSP) is typically locatable in cbfs. Select this
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option to manually attach the generated amdfw.rom outside of
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cbfs. The location is selected by the FWM position.
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config AMD_FWM_POSITION_INDEX
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int "Firmware Directory Table location (0 to 5)"
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range 0 5
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default 0 if BOARD_ROMSIZE_KB_512
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default 1 if BOARD_ROMSIZE_KB_1024
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default 2 if BOARD_ROMSIZE_KB_2048
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default 3 if BOARD_ROMSIZE_KB_4096
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default 4 if BOARD_ROMSIZE_KB_8192
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default 5 if BOARD_ROMSIZE_KB_16384
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help
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Typically this is calculated by the ROM size, but there may
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be situations where you want to put the firmware directory
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table in a different location.
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0: 512 KB - 0xFFFA0000
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1: 1 MB - 0xFFF20000
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2: 2 MB - 0xFFE20000
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3: 4 MB - 0xFFC20000
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4: 8 MB - 0xFF820000
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5: 16 MB - 0xFF020000
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comment "AMD Firmware Directory Table set to location for 512KB ROM"
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depends on AMD_FWM_POSITION_INDEX = 0
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comment "AMD Firmware Directory Table set to location for 1MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 1
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comment "AMD Firmware Directory Table set to location for 2MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 2
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comment "AMD Firmware Directory Table set to location for 4MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 3
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comment "AMD Firmware Directory Table set to location for 8MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 4
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comment "AMD Firmware Directory Table set to location for 16MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 5
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config DIMM_SPD_SIZE
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int
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default 512 # DDR4
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config RO_REGION_ONLY
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string
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depends on CHROMEOS
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default "apu/amdfw"
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config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
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int
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default 133
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config MAINBOARD_POWER_RESTORE
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def_bool n
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help
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This option determines what state to go to once power is restored
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after having been lost in S0. Select this option to automatically
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return to S0. Otherwise the system will remain in S5 once power
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is restored.
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endif # SOC_AMD_STONEYRIDGE
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