afa39105d8
This patch introduces x86_64 (64-bit) support to the payload, building upon the existing x86 (32-bit) architecture. Files necessary for 64-bit compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig option. BUG=b:242829490 TEST=Able to verify all valid combinations between coreboot and payload with this patch. Payload Entry Point Behavior with below code. +----------------+--------------------+----------------------------+ | LP_ARCH_X86_64 | Payload Entry Mode | Description | +----------------+--------------------+----------------------------+ | No | 32-bit | Direct protected mode init | +----------------+--------------------+----------------------------+ | Yes | 32-bit | Protected to long mode | +----------------+--------------------+----------------------------+ | Yes | 64-bit | Long mode initialization | +----------------+--------------------+----------------------------+ Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81968 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
106 lines
2.5 KiB
C
106 lines
2.5 KiB
C
/*
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* Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
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* Copyright (c) 2011 The ChromiumOS Authors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* From glibc-2.14, sysdeps/i386/memset.c */
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#include <stdint.h>
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#include "string.h"
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typedef uint32_t op_t;
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void *memset(void *dstpp, int c, size_t len)
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{
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int d0;
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unsigned long int dstp = (unsigned long int) dstpp;
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/* This explicit register allocation improves code very much indeed. */
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register op_t x asm("ax");
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x = (unsigned char) c;
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/* Clear the direction flag, so filling will move forward. */
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asm volatile("cld");
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/* This threshold value is optimal. */
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if (len >= 12) {
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/* Fill X with four copies of the char we want to fill with. */
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x |= (x << 8);
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x |= (x << 16);
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/* Adjust LEN for the bytes handled in the first loop. */
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len -= (-dstp) % sizeof(op_t);
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/*
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* There are at least some bytes to set. No need to test for
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* LEN == 0 in this alignment loop.
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*/
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/* Fill bytes until DSTP is aligned on a longword boundary. */
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asm volatile(
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"rep\n"
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"stosb" /* %0, %2, %3 */ :
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"=D" (dstp), "=c" (d0) :
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"0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) :
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"memory");
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/* Fill longwords. */
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asm volatile(
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"rep\n"
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"stosl" /* %0, %2, %3 */ :
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"=D" (dstp), "=c" (d0) :
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"0" (dstp), "1" (len / sizeof(op_t)), "a" (x) :
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"memory");
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len %= sizeof(op_t);
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}
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/* Write the last few bytes. */
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asm volatile(
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"rep\n"
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"stosb" /* %0, %2, %3 */ :
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"=D" (dstp), "=c" (d0) :
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"0" (dstp), "1" (len), "a" (x) :
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"memory");
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return dstpp;
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}
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void *memcpy(void *dest, const void *src, size_t n)
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{
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unsigned long d0, d1, d2;
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#if CONFIG(LP_ARCH_X86_64)
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asm volatile(
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"rep ; movsq\n\t"
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"mov %4,%%rcx\n\t"
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"rep ; movsb\n\t"
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: "=&c" (d0), "=&D" (d1), "=&S" (d2)
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: "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src)
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: "memory"
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);
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#else
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asm volatile(
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"rep ; movsl\n\t"
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"movl %4,%%ecx\n\t"
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"rep ; movsb\n\t"
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: "=&c" (d0), "=&D" (d1), "=&S" (d2)
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: "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src)
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: "memory"
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);
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#endif
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return dest;
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}
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