aade90e68d
This makes i82801ix use the common smm southbridge code to set up smm relocation and smi handler setup. This is needed in this change for the the smm relocation code relies on some southbridge functions provided in the common code. Some of the old code is kept for the Q35 qemu target. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Thinkpad X200: boots and going to and resuming from S3 still works fine. Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23419 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
48 lines
1.3 KiB
Plaintext
48 lines
1.3 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008-2009 coresystems GmbH
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## 2012 secunet security Networks AG
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SOUTHBRIDGE_INTEL_I82801IX
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bool
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select SOUTHBRIDGE_INTEL_COMMON
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
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select IOAPIC
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select HAVE_USBDEBUG
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select HAVE_HARD_RESET
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select USE_WATCHDOG_ON_BOOT
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select HAVE_SMI_HANDLER
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select HAVE_USBDEBUG_OPTIONS
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select SOUTHBRIDGE_INTEL_COMMON_GPIO
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select SOUTHBRIDGE_INTEL_COMMON_SMM
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select HAVE_INTEL_FIRMWARE if !BOARD_EMULATION_QEMU_X86_Q35
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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if SOUTHBRIDGE_INTEL_I82801IX
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config EHCI_BAR
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hex
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default 0xfef00000
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config HPET_MIN_TICKS
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hex
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default 0x80
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/i82801ix/bootblock.c"
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endif
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