b09e5001f3
* Adding separate targets for 32bit and 64bit qemu * Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv * rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage. This should probably be changed later. TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands: util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/31253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
178 lines
5.7 KiB
Makefile
178 lines
5.7 KiB
Makefile
################################################################################
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 The ChromiumOS Authors
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## Copyright (C) 2018 HardenedLinux
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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################################################################################
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################################################################################
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## RISC-V specific options
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################################################################################
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ifeq ($(CONFIG_ARCH_RISCV),y)
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ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
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check-ramstage-overlap-regions += stack
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endif
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riscv_flags = -I$(src)/arch/riscv/
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ifeq ($(CONFIG_ARCH_RISCV_RV64),y)
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_rv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64
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else
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ifeq ($(CONFIG_ARCH_RISCV_RV32),y)
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_rv_flags += -D__riscv -D__riscv_xlen=32 -D__riscv_flen=32
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else
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$(error "You need to select ARCH_RISCV_RV64 or ARCH_RISCV_RV32")
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endif
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endif
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ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
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riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
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else
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riscv_flags += $(_rv_flags)
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endif
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riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
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COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(riscv_flags) -print-libgcc-file-name)
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COMPILER_RT_romstage = $(shell $(GCC_romstage) $(riscv_flags) -print-libgcc-file-name)
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COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(riscv_flags) -print-libgcc-file-name)
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################################################################################
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## bootblock
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################################################################################
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ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y)
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bootblock-y = bootblock.S
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bootblock-y += trap_util.S
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bootblock-y += trap_handler.c
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bootblock-y += fp_asm.S
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bootblock-y += misaligned.c
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bootblock-y += sbi.c
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bootblock-y += mcall.c
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bootblock-y += virtual_memory.c
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bootblock-y += boot.c
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bootblock-y += smp.c
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bootblock-y += misc.c
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bootblock-$(ARCH_RISCV_PMP) += pmp.c
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bootblock-y += \
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$(top)/src/lib/memchr.c \
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$(top)/src/lib/memcmp.c \
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$(top)/src/lib/memcpy.c \
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$(top)/src/lib/memmove.c \
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$(top)/src/lib/memset.c
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bootblock-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
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$(objcbfs)/bootblock.debug: $$(bootblock-objs)
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
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-T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
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$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
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bootblock-c-ccopts += $(riscv_flags)
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bootblock-S-ccopts += $(riscv_asm_flags)
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ifeq ($(CONFIG_ARCH_RISCV_RV32),y)
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LDFLAGS_bootblock += -m elf32lriscv
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endif #CONFIG_ARCH_RISCV_RV32
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endif #CONFIG_ARCH_BOOTBLOCK_RISCV
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################################################################################
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## romstage
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################################################################################
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ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
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romstage-y += boot.c
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romstage-y += stages.c
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romstage-y += misc.c
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romstage-$(ARCH_RISCV_PMP) += pmp.c
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romstage-y += smp.c
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romstage-y += \
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$(top)/src/lib/memchr.c \
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$(top)/src/lib/memcmp.c \
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$(top)/src/lib/memcpy.c \
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$(top)/src/lib/memmove.c \
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$(top)/src/lib/memset.c
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romstage-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
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# Build the romstage
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$(objcbfs)/romstage.debug: $$(romstage-objs)
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
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romstage-c-ccopts += $(riscv_flags)
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romstage-S-ccopts += $(riscv_asm_flags)
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ifeq ($(CONFIG_ARCH_RISCV_RV32),y)
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LDFLAGS_romstage += -m elf32lriscv
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endif #CONFIG_ARCH_RISCV_RV32
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endif #CONFIG_ARCH_ROMSTAGE_RISCV
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################################################################################
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## ramstage
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################################################################################
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ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
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ramstage-y =
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ramstage-y += ramstage.S
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ramstage-y += mcall.c
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ramstage-y += trap_util.S
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ramstage-y += trap_handler.c
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ramstage-y += fp_asm.S
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ramstage-y += misaligned.c
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ramstage-y += sbi.c
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ramstage-y += virtual_memory.c
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ramstage-y += stages.c
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ramstage-y += misc.c
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ramstage-y += smp.c
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ramstage-y += boot.c
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ramstage-y += tables.c
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ramstage-y += payload.c
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ramstage-$(ARCH_RISCV_PMP) += pmp.c
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ramstage-y += \
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$(top)/src/lib/memchr.c \
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$(top)/src/lib/memcmp.c \
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$(top)/src/lib/memcpy.c \
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$(top)/src/lib/memmove.c \
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$(top)/src/lib/memset.c
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ramstage-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
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$(eval $(call create_class_compiler,rmodules,riscv))
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ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
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# Build the ramstage
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$(objcbfs)/ramstage.debug: $$(ramstage-objs)
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@printf " CC $(subst $(obj)/,,$(@))\n"
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$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
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ramstage-c-ccopts += $(riscv_flags)
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ramstage-S-ccopts += $(riscv_asm_flags)
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ifeq ($(CONFIG_ARCH_RISCV_RV32),y)
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LDFLAGS_ramstage += -m elf32lriscv
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endif #CONFIG_ARCH_RISCV_RV32
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endif #CONFIG_ARCH_RAMSTAGE_RISCV
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endif #CONFIG_ARCH_RISCV
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